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v3.0
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eX Fam i l y FP G A s
eX T i m i n g M o de l *
H a r d -W i re d C l o c k
External Setup = tINYH + tIRD1 + tSUD – tHCKH
= 0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns
Clock-to-Out (Pad-to-Pad), typical
=tHCKH + tRCO + tRD1 + tDHL
= 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
Ro ute d C l oc k
External Setup = tINYH + tIRD2 + tSUD – tRCKH
= 0.7 + 0.4 + 0.5 – 1.3= 0.3 ns
Clock-to-Out (Pad-to-Pad), typical
=tRCKH + tRCO + tRD1 + tDHL
= 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
*Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
I/O Module
t
INYH = 0.7 ns
t
IRD2 = 0.4 ns
t
IRD1 = 0.3 ns
Combinatorial
Cell
I/O Module
t
DHL = 2.6 ns
t
RD8 = 1.2 ns
t
RD4 = 0.7 ns
t
RD1 = 0.3 ns
t
PD = 0.7 ns
I/O Module
t
DHL = 2.6 ns
t
RD1 = 0.3 ns
t
RCO= 0.6 ns
I/O Module
t
INYH = 0.7 ns
t
ENZL= 1.9 ns
t
SUD = 0.5 ns
t
HD = 0.0 ns
t
SUD = 0.5ns
t
HD = 0.0 ns
t
RCKH= 1.3 ns
(100% Load)
t
IRD1 = 0.3 ns
DQ
Register
Cell
Routed
Clock
t
RD1 = 0.3 ns
t
RCO= 0.6 ns
t
HCKH= 1.1 ns
DQ
Register
Cell
Hard-Wired
Clock
I/O Module
t
DHL = 2.6 ns
t
ENZL= 1.9 ns
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