15.1.2.2.2 Powered-Off Protection

The source (Sx) pins of the device remain in the high impedance (Hi-Z) state, and the device performance

= 0 V or floating) or at a level that is below the undervoltage (UV) threshold. Powered-off protection minimizes

system design complexity by removing the need to control the system's power supply sequencing. The feature

prevents errant voltages on the input source pins from reaching the rest of the system and maintains isolation

when the system is powering up. Without powered-off protection, signal on the input source pins can back-power

the supply rails through internal ESD diodes and cause potential damage to the system.

A GND reference must always be present to ensure proper operation. Source and drain voltage levels of up to

±60 V are blocked in the powered-off condition.

15.1.2.2.3 Fail-Safe Logic

Fail-Safe logic circuitry allows voltages on the control input pin (DR) to be applied before the supply pins. This

eliminates the need for power sequencing of the logic signals and protects the device from potential damage.

The control inputs are protected against positive faults of up to +44 V in the powered-off condition, but do not

offer protection against a negative overvoltage condition.

15.1.2.2.4 Overvoltage Protection and Detection

The TMUX7462F detects overvoltage inputs by comparing the voltage on a source pin (Sx) with the fault

The switch automatically turns OFF and the source pin becomes high impedance to ensures only small leakage

currents flow through the switch when an overvoltage is detected. The drain pin (Dx) behavior can be adjusted

by controlling the drain response (DR) pin in the following ways:

If the DR pin is driven about VIH level of the pin, then the drain pin becomes high impedance (Hi-Z) upon

overvoltage fault.

If the DR pin is driven below VIL level of the pin, then the drain pin (Dx) is pulled to the supply that was

40 kΩ, and as a result, the drain current is limited to roughly 1 mA during a shorted load (to GND) condition.

15.1.2.2.5 Latch-Up Immunity

Latch-up is a condition where a low impedance path is created between a supply pin and ground. This condition

is caused by a trigger (current injection or overvoltage), but once activated, the low impedance path remains

even after the trigger is no longer present. This low impedance path may cause system upset or catastrophic

damage due to excessive current levels. The Latch-up condition typically requires a power cycle to eliminate the

low impedance path.

An insulating oxide layer is placed on top of the silicon substrate to prevent any parasitic junctions from forming

in the TMUX7462F devices. As a result, the devices are latch-up immune under all circumstances by device

construction.

www.ti.com

TMUX7462F

SCDS394 – MARCH 2021

Copyright © 2021 Texas Instruments Incorporated

Submit Document Feedback

21

Product Folder Links: TMUX7462F