ADN2807 datasheet(13/20 Pages) AD

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ADN2807

Rev. A | Page 13 of 20

100k

Ω 100kΩ

BUFFER

ADN2807

VCC/2

REFCLKN

REFCLKP

CRYSTAL

OSCILLATOR

XO1

XO2

REFSEL

19.44MHz

VCC

Figure 17. Crystal Oscillator Configuration

The ADN2807 can accept any of the following reference clock

frequencies: 19.44 MHz, 38.88 MHz, and 77.76 MHz at LVTTL/

LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/

LVDS levels via the REFCLKN/P inputs, independent of data

rate. The input buffer accepts any differential signal with a

peak-to-peak differential amplitude of greater than 100 mV

(e.g., LVPECL or LVDS) or a standard single-ended low voltage

TTL input, providing maximum system flexibility. The

appropriate division ratio can be selected using the REFSEL0/1

pins according to Table 6. Phase noise and duty cycle of the

reference clock are not critical, and 100 ppm accuracy is

sufficient.

An on-chip oscillator to be used with an external crystal is also

provided as an alternative to using the REFCLKN/P inputs.

Details of the recommended crystal are given in Table 7.

Table 6. Reference Frequency Selection

REFSEL

REFSEL[1..0]

Applied Reference

Frequency (MHz)

19.44

38.88

77.76

155.52

REFCLKP/N Inactive. Use 19.44 MHz

XTAL on Pins XO1, XO2 (Pull REFCLKP

to VCC)

Table 7. Required Crystal Specifications

Parameter

Value

Mode

Series Resonant

Frequency/Overall Stability

19.44 MHz ± 100 ppm

Frequency Accuracy

±100 ppm

Temperature Stability

±100 ppm

Aging

±100 ppm

ESR

50 Ω max

REFSEL must be tied to VCC when the REFCLKN/P inputs are

active or to VEE when the oscillator is used. No connection

between the XO pin and REFCLK input is necessary (Figure 15

to Figure 17). Note that the crystal should operate in series

resonant mode, which renders it insensitive to external

parasitics. No trimming capacitors are required.

LOCK DETECTOR OPERATION

The lock detector monitors the frequency difference between

the VCO and the reference clock and deasserts the loss-of-lock

signal when the VCO is within 500 ppm of center frequency.

This enables the phase loop, which then maintains phase lock,

unless the frequency error exceeds 0.1%. Should this occur, the

loss-of-lock signal is reasserted and control returns to the

frequency loop, which will reacquire and maintain a stable clock

signal at the output. The frequency loop requires a single

external capacitor between CF1 and CF2. The capacitor

specification is given in Table 8.

Table 8. Recommended CF Capacitor Specification

Parameter

Value

Temperature Range

–40°C to +85°C

Capacitance

>3.0 µF

Leakage

<80 nA

Rating

>6.3 V

1000

500

1000

fVCO ERROR

(ppm)

LOL

Figure 18. Transfer Function of LOL

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