ADN2807

Rev. A | Page 17 of 20

CHOOSING AC COUPLING CAPACITORS

The ac coupling capacitors at the input (PIN, NIN) and output

(DATAOUTP, DATAOUTN) of the ADN2807 must be chosen

so that the device works properly at both OC-3 and OC-12 data

rates. When choosing the capacitors, the time constant formed

with the two 50 Ω resistors in the signal path must be

considered. When a large number of consecutive identical digits

(CIDs) are applied, the capacitor voltage can drop due to

baseline wander (Figure 23), causing pattern dependent jitter

(PDJ). For the ADN2807 to work robustly at both OC-3 and

OC-12, a minimum capacitor of 0.1 µF to PIN/NIN and 0.1 µF

on DATAOUTP/DATAOUTN should be used. This is based on

the assumption that 1000 CIDs must be tolerated, and that the

PDJ should be limited to 0.01 UI p-p.

DC-COUPLED APPLICATION

The inputs to the ADN2807 can also be dc-coupled. This may

be necessary in burst mode applications where there are long

periods of CIDs, and where baseline wander cannot be

tolerated. If the inputs to the ADN2807 are dc-coupled, care

must be taken not to violate the input range and common-mode

level requirements of the ADN2807 (Figure 24 to Figure 26). If

dc coupling is required and the output levels of the TIA do not

adhere to the levels shown in Figure 25 and Figure 26, there

must be level shifting and/or an attenuator between the TIA

outputs and the ADN2807 inputs.

LOL TOGGLING DURING LOSS OF INPUT DATA

If the input data stream is lost due to a break in the optical link

(or for any reason), the clock output from the ADN2807 stays

within 1000 ppm of the VCO center frequency as long as there

is a valid reference clock. The LOL pin will toggle at a rate of

several kHz. This is because the LOL pin will toggle between a

Logic 1 and Logic 0 while the frequency loop and phase loop

swap control of the VCO. The chain of events is as follows:

•

The ADN2807 is locked to the input data stream; LOL = 0.

•

The input data stream is lost due to a break in the link. The

VCO frequency drifts until the frequency error is greater

than 1000 ppm. LOL is asserted to a Logic 1 as control of

the VCO is passed back to the frequency loop.

•

The frequency loop pulls the VCO to within 500 ppm of its

center frequency. Control of the VCO is passed back to the

phase loop and LOL is deasserted to Logic 0.

•

The phase loop tries to acquire, but there is no input data

present so the VCO frequency drifts.

•

The VCO frequency drifts until the frequency error is

greater than 1000 ppm. LOL is asserted to a Logic 1 as

control of the VCO is passed back to the frequency loop.

This process is repeated until a valid input data stream is

re-established.

50

Ω

ADN2807

NIN

PIN

50

Ω

V2

V1

V2b

V1b

TIA

LIMAMP

CDR

DATAOUTP

DATAOUTN

+

4

3

2

1

V1

V1b

V2

V2b

VTH = ADN2807 QUANTIZER THRESHOLD

VTH

NOTES

1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0.

2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b

3. WHEN THE BURST OF DATA STARTS AGAIN,THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS,

CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON

THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELLED OUT. THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE.

4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2807. THE QUANTIZER WILL BE

ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.

Figure 23. Example of Baseline Wander