AX88852 datasheet(29/39 Pages) ASIX

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AX88850

PRELIMINARY

ASIX ELECTRONICS CORPORATION

4.5 Configuration Register (CONFIG)

Page 0 to Page 3 Address 0h

Bit

Bit Name

Access

Bit Description

D15-D8

Reserved

Written as “0” for future compatibility concern.

Undefined by read.

RST_FLAG

Reset Flag : The bit is set when power on reset and is clear after read

CONFIG register.

RID_CH

Repeater ID Changed : The bit is set when Daisy-Chain RID input

override the current RID or after power on reset. When read CONFIG

DIS_CIPHER

R/W

Disable Cipher Function : Then set the bit at PCS mode, the 5bit symbol

scramble and descrambler function are disable. Default is enable.

MGTEN

R/W

Management Enable : This bit enable all the management counters.

0 : Management Counters disabled. (default)

1 : Management Counters enabled.

COL_LIMIT32

R/W

Collision limit : This bit configures the collision limit for Auto-

Partitioning.

0 : Consecutive Collision limit set to 64 (default). A port will

be partitioned on the 65th consecutive collision.

1 : Consecutive Collision limit set to 32 . A port will

be partitioned on the 33rd consecutive collision.

DIS_PART

R/W

Disable Auto-Partition : Set this bit disable the Auto-Partition

algorithm.

0 : Auto-Partition is not disabled (default)

1 : Auto-Partition is disabled .

PHY_ACCESS

R/W

PHY access enable : This bit enable to access PHY register via MII serial

protocol.

0 : PHY access disabled (default)

1 : PHY access enabled .

RST_RSM

R/W

Reset Repeater State Machines : Setting the bit holds the RSM in reset.

The management event flags and counters are unaffected by this bit.

Setting this bit while a reception is in progress may truncate the packet.

0 : AX88850 in normal operation (default)

1 : AX88850 held in reset .

4.6 Page Register (PAGE)

Page 0 to Page 3 Address 1h

Bit

Bit Name

Access

Bit Description

D15-D8

GEP[3:0]

R/W

D11-D8 : GEP I/O control. Default = 0h for input mode. Otherwise, =1h,

enable output.

D15-D12 : GEP Data . Default = 0h.

When write, D15-D12 value present to GEP[3:0] if enabled.

When read, D15-D12 reflect the GEP[3:0] value.

D7-D2

Reserved

Written as “0” for future compatibility concern.

undefined by read.

D1-D0

PAGE[1:0]

R/W

Those bits setting the register page to be accessed.

PAGE[1:0]

PAGE

(default)

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