M34E02 datasheet(8/23 Pages) STMICROELECTRONICS

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M34E02

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Figure 6. Result of Setting the Write Protection

Setting the Write-Protection

The M34E02 has a hardware write-protection

feature, using the Write Control (WC) signal. This

signal can be driven High or Low, and must be

held constant for the whole instruction sequence.

When Write Control (WC) is held High, the whole

memory array (addresses 00h to FFh) is write

protected. When Write Control (WC) is held Low,

the write protection of the memory array is

dependent on whether software write-protection

has been set.

Software write-protection allows the bottom half of

the memory area (addresses 00h to 7Fh) to be

write protected irrespective of subsequent states

of the Write Control (WC) signal.

Software write-protection is handled by three in-

structions:

– SWP: Set Write Protection

– CWP: Clear Write Protection

– PSWP: Permanently Set Write Protection

The level of write-protection (set or cleared) that

has been defined using these instructions, re-

mains defined even after a power cycle.

SWP and CWP. If the software write-protection

has been set with the SWP instruction, it can be

cleared again with a CWP instruction.

The two instructions (SWP and CWP) have the

same format as a Byte Write instruction, but with a

different Device Type Identifier (as shown in Table

2). Like the Byte Write instruction, it is followed by

an address byte and a data byte, but in this case

the contents are all “Don’t Care” (Figure 7). Anoth-

er difference is that the voltage, VHV, must be ap-

plied on the E0 pin, and specific logical levels must

be applied on the other two (E1 and E2, as shown

in Table 2).

PSWP. If the software write-protection has been

set with the PSWP instruction, the first 128 bytes

of the memory are permanently write-protected.

This write-protection cannot be cleared by any in-

struction, or by power-cycling the device, and re-

gardless the state of Write Control (WC). Also,

once the PSWP instruction has been successfully

executed, the M34E02 no longer acknowledges

any instruction (with a Device Type Identifier of

0110) to access the write-protection settings.

Figure 7. Setting the Write Protection (WC = 0)

Default EEPROM memory area

state before write access

to the Protect Register

AI01936C

Standard

Array

FFh

Standard

Array

80h

7Fh

00h

Standard

Array

FFh

Write

Protected

Array

80h

7Fh

00h

State of the EEPROM memory

area after write access

to the Protect Register

Memory

Area

SDA LINE

AI01935B

ACK

WORD

ADDRESS

VALUE

(DON'T CARE)

ACK

DATA

VALUE

(DON'T CARE)

ACK

CONTROL

BYTE

BUS ACTIVITY

MASTER

BUS ACTIVITY

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