M34E02 datasheet(12/23 Pages) STMICROELECTRONICS

12 / 23 page

M34E02

12/23

Sequential Read

This operation can be used after a Current Ad-

dress Read or a Random Address Read. The bus

master

does acknowledge the data byte output,

and sends additional clock pulses so that the de-

vice continues to output the next byte in sequence.

To terminate the stream of bytes, the bus master

must

not acknowledge the last byte, and must

generate a Stop condition, as shown in Figure 10.

The output data comes from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’,

and the device continues to output data from

memory address 00h.

Acknowledge in Read Mode

For all Read commands, the device waits, after

each byte read, for an acknowledgment during the

9th bit time. If the bus master does not drive Serial

Data (SDA) Low during this time, the device termi-

nates the data transfer and switches to its Stand-

by mode.

INITIAL DELIVERY STATE

The device is delivered with the memory array

erased: all bits are set to 1 (each byte contains

FFh).

USE WITHIN A DDR2 DIMM

In the application, the M34E02 is soldered directly

in the printed circuit module. The three Chip

Enable inputs (E0, E1, E2) must be connected to

VSS or VCC directly (that is without using a pull-up

or pull-down resistor) through the DIMM socket

(see Table 4.). The pull-up resistors needed for

normal behavior of the I2C bus are connected on

the I2C bus of the mother-board (as shown in

Figure 11).

The Write Control (WC) of the M34E02 can be left

unconnected. However, connecting it to VSS is

recommended, to maintain full read and write

access.

Table 4. DRAM DIMM Connections

Programming the M34E02

The situations in which the M34E02 is pro-

grammed can be considered under two headings:

– when the DDR2 DIMM is isolated (not inserted

on the PCB motherboard)

– when the DDR2 DIMM is inserted on the PCB

motherboard

DDR2 DIMM Isolated. With

specific

program-

ming equipment, it is possible to define the

M34E02 content, using Byte and Page Write in-

structions, and its write-protection using the SWP

and CWP instructions. To issue the SWP and

CWP instructions, the DDR2 DIMM must be insert-

ed in the DDR2-specific slot where the E0 signal

can be driven to VHV during the whole instruction.

This programming step is mainly intended for use

by DDR2 DIMM makers, whose end application

manufacturers will want to clear this write-protec-

tion with the CWP on their own specific program-

ming equipment, to modify the lower 128 Bytes,

and finally to set permanently the write-protection

with the PSWP instruction.

DDR2 DIMM Inserted in the Application Mother

Board. As the final application cannot drive the

E0 pin to VHV, the only possible action is to freeze

the write-protection with the PSWP instruction.

Table 5 and Table 6 show how the Ack bits can be

used to identify the write-protection status.

DIMM Position

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

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