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High Speed CMOS Logic – 54HC373

Rev 1.0

10/03/21

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2V

0.1

0.1

0.1

4.5V

0.1

0.1

0.1

6.0V

0.1

0.1

0.1

V

4.5V

0.26

0.33

0.40

V

Maximum Low-Level

Output Voltage

6.0V

0.26

0.33

0.40

V

Maximum Input

Leakage Current

6.0V

or GND

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Current

6.0V

or GND,

4

40

160

µA

Maximum Three-State

Leakage Current

6.0V

Output in

High-

Impedance

State,

GND

±0.5

±5.0

±10.0

µA

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

125

155

190

4.5V

25

31

38

Maximum

Propagation Delay,

D to Q, (Figure 1,5)

6.0V

21

26

32

ns

2.0V

140

175

210

4.5V

28

35

42

Maximum

Propagation Delay,

LE to Q, (Figure 2,5)

6.0V

24

30

36

ns

2.0V

150

190

225

4.5V

30

38

45

Maximum

Propagation Delay,

OE to Q (Figure 3,6)

6.0V

26

33

38

ns

2.0V

150

190

225

4.5V

30

38

45

Maximum

Propagation Delay,

OE to Q (Figure 3,6)

6.0V

26

33

38

ns

5 Not production tested in die form, characterized by chip design