SII164 datasheet(13/33 Pages) SILICONIMAGE

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SiI 164 PanelLink Transmitter

Data Sheet

SiI-DS-0021-C

Pin Descriptions (cont’d)

Configuration Pins

Pin Name Pin # Type Description

MSEN

Out

Monitor Sense. This pin is an open collector output. The behavior of this output depends on

whether I

2C interface active:

2C bus inactive (ISEL/RST# = LOW)

HIGH level indicates a powered on receiver is detected at the differential outputs.

A LOW level indicates a powered on receiver is not detected.

2C bus is enabled (ISEL/RST# = HIGH)

The output is programmable through the I

2C interface (see I2C Register Definitions).

An external 5K pull-up resistor to VDDQ is required on this pin.

ISEL/RST#

2C Interface Select.

ISEL/RST#=HIGH,

2C interface is active.

ISEL/RST#=LOW,

2C is inactive and the chip configuration is read from the configuration strapping pins. This pin

also acts as an asynchronous reset to the I

2C interface controller. The reset is active when this

input is held LOW.

Note: When the I

2C interface is active, DKEN must be set HIGH.

BSEL/SCL

Input bus select / I

2C clock. This pin is an open collector input. If I2C bus is enabled

(ISEL/RST# = HIGH), then this pin is the I

2C clock input. If the I2C is disabled (ISEL/RST# =

LOW), then this pin selects the input bus width.

Input Bus Select:

HIGH selects 24-bit input mode

LOW selects 12-bit input mode

DSEL/SDA

In/Out Dual edge clock select / I

2C Data. This pin is an open collector input/output. If I2C bus is

enabled (ISEL/RST# = HIGH), then this pin is the I

2C data line. If the I2C bus is disabled

(ISEL/RST# = LOW), then this pin selects whether single clock dual edge is used.

Dual Edge clock select:

When HIGH, IDCK+ latches input data on both falling and rising clock edges.

When LOW, IDCK+/IDCK- latches input data on only falling or rising clock edges.

In 24-/12-bit mode:

If HIGH (dual edge), IDCK+ is used to latch data on both falling and rising edges.

If LOW (single edge), IDCK+ latches 1

st half data and IDCK- latches 2nd half data.

EDGE/

HTPLG

Edge select / Hot Plug input. If the I

2C bus is enabled (ISEL/RST# = HIGH), then this pin is

used to monitor the “Hot Plug” detect signal (Please refer to the DVI

TM or VESA® P&DTM and

DFP standards). This Input is ONLY 3.3V tolerant and has no internal de-bouncer circuit.

If I

2C bus is disabled (ISEL/RST# = LOW), then this pin selects the clock edge that will latch

the data. How the EDGE setting works depends on whether dual or single edge latching is

selected:

Dual Edge Mode (DSEL = HIGH)

EDGE = LOW, the primary edge (first latch edge after DE is asserted) is the falling edge.

EDGE = HIGH, the primary edge (first latch edge after DE is asserted) is the rising edge.

Note: In 24-bit Single Clock Dual Edge mode, EDGE is ignored.

Single Edge Mode (DSEL = LOW)

EDGE = LOW, the falling edge of the clock is used to latch data.

EDGE = HIGH, the rising edge of the clock is used to latch data.

DKEN

De-skewing enable.

2C mode (ISEL/RST# = HIGH)

DKEN pin must be set to HIGH. DK[3:1] pins are ignored and the De-skewing increments are

selected through the I

2C interface (see the I2C register definitions).

Non I

2C mode (ISEL/RST# = LOW)

DKEN = LOW, then default De-skewing setting is used.

DKEN = HIGH, then DK[3:1] is used as the De-skewing setting. The De-skewing increments

are TSTEP. Please see Data De-skew Feature for an illustration.

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