SiI 164 PanelLink Transmitter

Data Sheet

17

SiI-DS-0021-C

I

To program the SiI 164 in data latched on 12 bit mode Dual Edge Clock with Primary Edge as the rising edge, De-

skew enabled without Hotplug and the following sample programming sequence listed in Table 1 may be used. It is

important to note that the suggested I

Table 1. Sample Programming Sequence for SiI 164

Register(Hex)

Value(Hex)

Description

0x08

31

Enable HEN, VEN, 1

rising edge with PD low until all

registers are programmed.

0x09

00

MSEN disabled.

0x0A

90

De-skew enabled with default 100

value. CTL is not used.

0x0C

89

SCNT, PLL Filter Enable and PLL

Bandwidth Filter set to default.

0x08

33

Set PD to High after the registers above

have been programmed.

Enabling Hot Plug Detection Mode

As documented in the VESA Digital Flat Panel Standard, all monitors are required to support Hot Plug Detection

but support is optional for the host. The SiI 164 supports the Hot Plug Detect feature. In I

as HTPLG input. It should be noted that the HTPLG pin on the SiI 164 is only 3.3V tolerant therefore HTPLG

voltage level from the DVI connector should be level shifted or clamped at 3.3V.

When the voltage level at the HTPLG pin is 3.3V, the HTPLG bit will be set to 1. To output the HTPLG bit via the

MSEN pin, register MSEL[2:0] should be programmed to 011.

The SiI 164 can also be programmed to enable the Hot Plug Detection Mode via the Receiver Sense function. In

this mode, HTPLG pin is not required. By programming MSEL[2:0] to 010, SiI 164 will output the RSEN=1 bit

though the MSEN pin when the SiI 164 is connected to a powered receiver.