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NB6L16DR2 Datasheet(PDF) 7 Page - ON Semiconductor

Part # NB6L16DR2
Description  2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/Driver/Translator Buffer
PDF  12 Pages
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

NB6L16DR2 Datasheet(HTML) 7 Page - ON Semiconductor

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NB6L16
http://onsemi.com
7
Table 7. AC CHARACTERISTICS VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 18)
−40
°C
25
°C
85
°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
VOUTPP
Output Voltage Amplitude
fin < 3 GHz
(See Figures 2 & 3)
fin < 6 GHz
500
270
700
350
500
270
700
350
500
270
700
300
mV
tPLH,
tPHL
Propagation Delay to
Output Differential @ 1 GHz
80
130
180
80
130
180
85
135
185
ps
tSKEW
Duty Cycle Skew (Note 19)
Device−to−Device Skew
3
30
25
60
3
30
25
60
3
30
25
60
ps
tJITTER
RMS Random Clock Jitter
(Note 20)
fin < 6 GHz
Peak−to−Peak Data Dependent JItter
(Note 21)
fin < 6 Gb/s
0.2
2
1
12
0.2
2
1
12
0.2
2
1
12
ps
VINPP
Input Voltage Swing / Sensitivity
(Differential Configuration) (Note 22)
75
700
2500
75
700
2500
75
700
2500
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% − 80%)
30
70
120
30
70
120
30
70
120
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
18. Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50
W to VCC. Input edge rates 40 ps (20% − 80%).
19. See Figure 9 tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical
transitions and conditions @ 1 GHz.
20. Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
21. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 223−1 data rate at 6 Gb/s.
22. VINPP(max) cannot exceed VCC − VEE. (Applicable only when VCC − VEE < 2500 mV). Input voltage swing is a single−ended measurement
operating in the differential mode.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
1
2
3
4
5
678
INPUT CLOCK FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP)
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 3.3 V
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
12
34
5
6
7
8
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP)
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 2.5 V
85
°C
−40
°C
25
°C
−40
°C
25
°C
85
°C



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