TMS320DM6443 datasheet(39/202 Pages) TI

39 / 202 page

www.ti.com

TMS320DM6443

Digital Media System on-Chip

SPRS282 – DECEMBER 2005

Table 2-18. VLYNQ Terminal Functions

SIGNAL

IPD/

TYPE(1)

DESCRIPTION

IPU(2)

NAME

NO.

VLYNQ

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

EM_CS5/

Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or

GPIO8/

I/O/Z

IPD

NAND flash.

VLYNQ_CLOCK

For GPIO, it is GPIO pin 8 GPIO8

For VLYNQ, it is the clock (VLYNQ_CLOCK).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

EM_CS4/

Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or

GPIO9/

I/O/Z

IPD

NAND flash.

VLYNQ_SCRUN

For GPIO, it is GPIO9.

For VLYNQ, it is the Serial Clock run request (VLYNQ_SCRUN).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

EM_A[15]/

address bit 15 output EM_A[15].

GPIO16/

I/O/Z

IPD

For GPIO, it is GPIO16.

VLYNQ_TXD3

For VLYNQ, it is transmit bus bit 3 output VLYNQ_TXD3.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

EM_A[17]/

address bit 17 output EM_A[17].

GPIO14/

I/O/Z

IPD

For GPIO, it is GPIO14.

VLYNQ_TXD2

For VLYNQ, it is transmit bus bit 2 output VLYNQ_TXD2.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

EM_A[19]/

address bit 19 output EM_A[19].

GPIO12/

I/O/Z

IPD

For GPIO, it is GPIO12.

VLYNQ_TXD1

For VLYNQ, it is transmit bus bit 1 output VLYNQ_TXD1.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

EM_A[21]/

address bit 21 output EM_A[21].

GPIO10/

I/O/Z

IPD

For GPIO, it is GPIO10.

VLYNQ_TXD0

For VLYNQ, it is bit 0 of the transmit bus (VLYNQ_TXD0).

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

EM_A[14]/

address bit 14 output EM_A[14].

GPIO17/

I/O/Z

IPD

For GPIO, it is GPIO17.

VLYNQ_RXD3

For VLYNQ, it is receive bus bit 3 input VLYNQ_RXD3.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

EM_A[16]/

address bit 16 output EM_A[16].

GPIO15/

I/O/Z

IPD

For GPIO, it is GPIO15.

VLYNQ_RXD2

For VLYNQ, it is receive bus bit 2 input VLYNQ_RXD2.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

EM_A[18]/

address bit 18 output EM_A[18].

GPIO13/

I/O/Z

IPD

For GPIO, it is GPIO13.

VLYNQ_RXD1

For VLYNQ, it is receive bus bit 1 input VLYNQ_RXD1.

This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is

EM_A[20]/

address bit 20 output EM_A[20].

GPIO11/

I/O/Z

IPD

For GPIO, it is GPIO11.

VLYNQ_RXD0

For VLYNQ, it is receive bus bit 0 input VLYNQ_RXD0.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k

Ω resistor should be used.)

Table 2-19. VPBE Terminal Functions

SIGNAL

IPD/

TYPE(1)

DESCRIPTION

IPU(2)

NAME

NO.

VIDEO OUT (VPBE)

HSYNC

C17

I/O/Z

IPD

VPBE Horizontal Synch Output

VSYNC

C18

I/O/Z

IPD

VPBE Vertical Synch Output

VCLK

D19

I/O/Z

IPD

VPBE Clock Output

VPBECLK

C19

I/O/Z

IPD

VPBE Clock Input

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. (To pull up a signal to the opposite supply rail, a 1-k

Ω resistor should be used.)

Device Overview

TMS320DM6443 Datasheet(PDF) 39 Page - Texas Instruments

TMS320DM6443 Datasheet(HTML) 39 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL