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ADGS1612 Datasheet(PDF) 20 Page - Analog Devices |
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ADGS1612 Datasheet(HTML) 20 Page - Analog Devices |
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20 / 29 page ![]() ADGS1612 Data Sheet Rev. 0 | Page 20 of 29 VDD VDD VSS VSS 0.1µF 0.1µF GND INPUT LOGIC RL1 300Ω CL1 35pF VS1 S1 D1 VOUT1 VOUT1 VOUT2 RL 300Ω CL2 35pF VS2 S2 D2 VOUT2 SCLK 50% 80% 80% 80% 80% 50% 0V 0V 0V tD tD Figure 35. Break-Before-Make Time Delay, tD VDD VSS VDD VSS 0.1µF 0.1µF GND RL 300Ω CL 35pF VS INPUT LOGIC Sx Dx VOUT SCLK VOUT 50% 50% 90% 10% tON tOFF Figure 36. Switching Times VDD VSS VDD VSS GND INPUT LOGIC CL 1nF SD VOUT RS VS SYNC 3V VOUT ∆VOUT QINJ = CL × ∆VOUT SWITCH OFF SWITCH ON Figure 37. Charge Injection AC PSRR = 20 log VOUT GND D1 S1 NIC NETWORK ANALYZER NOTES 1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED FROM THE AC PSRR MEASUREMENT. RL 50Ω RL 50Ω VS VOUT VS VDD VSS VSS INTERNAL BIAS Figure 38. AC PSRR |
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