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UPD16705 Datasheet(PDF) 8 Page - NEC

Part # UPD16705
Description  263/256-OUTPUT TFT-LCD GATE DRIVER
PDF  12 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

UPD16705 Datasheet(HTML) 8 Page - NEC

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Data Sheet S15818EJ1V0DS
8
µµµµPD16705
Electrical Characteristics (TA =
−−−−20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −−−−10 V, VSS = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
Note
MAX.
Unit
High-level Input Voltage
VIH
0.8 VDD1
VDD1
V
Low-level Input Voltage
VIL
CLK, STVR (STVL), R,/L,
OE1 to OE3
VSS
0.2 VDD1
V
High-level Output Voltage
VOH
STVR (STVL), IOH =
−40
µAVDD1 −0.4
VDD1
V
Low-level Output Voltage
VOL
STVR (STVL), IOL = +40
µAVSS
VSS +0.4
V
LCD Driver Output ON Resistance
RON
VOUT = VEE +1.0 V, or
VDD2
−1.0 V
0.33
1.0
k
Ω
Pull-up Resistance
RPU
VDD1 = 3.3 V, /AO, MODE
10
50
100
k
Ω
Input Leak Current
IIL
VI = 0 V or 3.6 V,
except for /AO, MODE
±1.0
µA
Static Current Dissipation
IDD1
VDD1, fCLK = 50 kHz,
OE1 = OE2 = OE3 = L,
fSTV = 60 Hz, no load
390
1000
µA
IDD2
VDD2, fCLK = 50 kHz,
OE1 = OE2 = OE3 = L,
fSTV = 60 Hz, no load
10
100
µA
IEE
VEE, fCLK = 50 kHz,
OE1 = OE2 = OE3 = L,
fSTV = 60 Hz, no load
−1100
−400
µA
Remark STV: STVR (STVL).
Switching Characteristics (TA =
−−−−20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −−−−10 V, VSS = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Cascade Output Delay Time
tPHL1
CL = 20 pF,
800
ns
tPLH1
CLK
→ STVL (STVR)
800
ns
Driver Output Delay Time
tPHL2
CL = 300 pF, CLK
→ On
500
ns
tPLH2
500
ns
tPHL3
CL = 300 pF, OEn
→ On
800
ns
tPLH3
800
ns
Output Rise Time
tTLH
CL = 300 pF
800
ns
Output Fall Time
tTHL
800
ns
Input Capacitance
CI
TA = 25°C
15
pF
Timing Requirements (TA =
−−−−20 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 23 V, VEE = −−−−10 V, VSS = 0 V,
tr = tf = 20 ns (10 to 90%))
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Clock Pulse High Width
PWCLK(H)
500
ns
Clock Pulse Low Width
PWCLK(L)
500
ns
Enable Pulse Width
PWOE
1000
ns
Data Setup Time
tSETUP
STVR (STVL)
↑ → CLK ↑
200
ns
Data Hold Time
tHOLD
CLK
↑ → STVR (STVL) ↓
200
ns
Remark Unless otherwise specified, the input level is defined to be VIH = 0.8 VDD1, VIL = 0.2 VDD1.



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