Preliminary Technical Data

ADRF5301

Rev. PrB | Page 7 of 9

THEORY OF OPERATION

The ADRF5301 integrates a negative voltage generator (NVG)

and requires a single positive supply voltage applied to the VDD

pin. Bypassing capacitors are recommended on the supply line

to minimize RF coupling.

All of the RF ports (RFC, RF1, and RF2) are dc-coupled to 0 V,

and no dc blocking is required at the RF ports when the RF line

potential is equal to 0 V. The RF ports are internally matched to

50 Ω. Therefore, external matching networks are not required.

The ADRF5301 integrates a driver to perform logic functions

internally and to provide the user with the advantage of a simplified

control interface. The driver features a single digital control

input pin, CTRL, which controls the state of the RF paths. The

logic level applied to the CTRL pin determines which RF port is

in the insertion loss state while the other path is in the isolation

state (see Table 5).

Table 5. Control Voltage Truth Table

Digital Control Input

RF Paths

CTRL

RF1 to RFC

CTRL

High

Insertion loss (on)

Isolation (off)

Low

Isolation (off)

Insertion loss (on)

The insertion loss path conducts the RF signal between the

selected RF throw port and the RF common port. The switch

design is bidirectional with equal power handling capabilities.

The RF input signal can be applied to the RFC port or the

selected RF throw port. The isolation paths provide high loss

between the insertion loss path and the unselected RF throw

port that is reflective.

The ideal power-up sequence is as follows:

1. Connect GND reference.

2. Power up supply input VDD.

3. Apply digital control input CTRL. Applying the CTRL

control before applying the VDD supply inadvertently forward

biases and damages the internal ESD protection structures. To

avoid this damage, use a series 1 kΩ resistor to limit the current

flowing into the control pin. Use pull-up or pull-down resistors

if the controller output is in a high impedance state after VDD

is powered up and the control pins are not driven to a valid

logic state

4. Apply RF input signal.

The ideal power-down sequence is the reverse order of the

power-up sequence.