ADRF6658BCPZ datasheet(13/31 Pages) AD

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Data Sheet

ADRF6658

Rev. A | Page 13 of 31

THEORY OF OPERATION

DUAL MIXER CORES

The ADRF6658 provides two double balanced active mixers

based on the Gilbert cell design. The RF inputs, LO inputs, and

IF outputs of the mixers are all differential, providing maximum

usable bandwidth at the input and output ports. The mixers are

designed for a 50 Ω input impedance and a 300 Ω output

impedance, with external RF chokes connected to the supply.

Mixer RF Inputs

At the RF input of each channel (MIXARFIN and MIXBRFIN) of

the ADRF6658, a tunable balun converts the single-ended input

signal into differential form, to be fed into the mixer section.

The tuning of the balun is controlled by the two sets of register

bits: RF balun input cutoff (CIN) in Register 13, Bits[DB12:DB10],

and RF balun output cutoff (COUT) in Register 13, Bits[DB9:DB7].

Mixers Bias Circuit

A band gap reference circuit generates the reference currents

used by mixers. The bias current for the LO circuit of the

mixers can be programmed via the mixer LO IBIAS bits in

RF Voltage to Current (V to I) Converter

The differential RF input signal, created in the internal balun

from the external, single-ended RF signal provided to the

MIXARFIN or MIXBRFIN pin, is applied to a V to I converter that

converts the differential input voltage to output currents. The

V to I converter provides a 50 Ω input impedance. The V to I

section bias current can be adjusted up or down using the mixer

V to I IBIAS bits in Register 13, Bits[DB24:DB22]. Adjusting the

current up improves IIP3 and P1dB input, but degrades the SSB

NF. Adjusting the current down improves the SSB NF but

degrades IIP3 and the input P1dB. The conversion gain remains

nearly constant over a wide range of mixer V to I IBIAS settings,

allowing the device to be adjusted dynamically without

affecting the conversion gain. A setting of 3 or 4 provides a

good trade-off of IP3 and SSB NF.

Mixer Power-Down

It is possible to power down either mixer by programming the

relevant bits. For Channel A, program the Mixer A enable bit

(Bit DB5 in Register 13). For Channel B, program the Mixer B

Enable bit (Bit DB4 in Register 13). The mixers can be powered

down independently.

Mixer Output

The mixer load uses a pair of 150 Ω resistors connected to the

positive supply. This provides a 300 Ω differential output resistance,

which matches the input impedance of the internal IF DGA

block. Pull the mixer outputs to the positive supply externally

using a pair of RF chokes, or by using an output transformer

with the center tap connected to the positive supply. The mixer

outputs are dc-coupled, and they can operate up to

approximately 500 MHz into a 300 Ω load.

DGA BASIC STRUCTURE

In each channel, the ADRF6658 has a built-in, variable gain

DGA. Each amplifier consists of a digitally controlled, passive

attenuator of a 300 Ω differential input impedance followed by a

highly linear transconductance amplifier with feedback. The

output impedance of the gain amplifier is 100 Ω, differentially.

The input impedance of the DGA block matches the output

impedance of the internal mixer.

The gain of each amplifier can be programmed independently,

either via the DGA control bits in the serial control registers, or

via an external, 6-bit parallel port. The choice of serial or

parallel control is determined by the DGA control select bit, Bit

DB22 in Register 7. Programming this bit to 0 allows the gain to

be set by programming Register 14 (Bits[DB17:DB12] for

Channel A, or Bits[DB11:DB6] for Channel B). When the DGA

Control Select bit is set to 1, the gain is set by the binary value

applied to the 6-bit, external parallel control interface (Pin A5

through Pin A0 for Channel A, or Pin B5 through Pin B0 for

Channel B).

Figure 23. Simplified Schematic

Input System

The dc voltage level at the inputs of each amplifier is set to

approximately 1.1 V by two independent internal voltage

reference circuits. These reference circuits are not accessible and

cannot be adjusted.

Power down each amplifier by setting Bit DB5 and Bit DB4.in

amplifier reduces to 10 μA (typical). The dc level at the inputs

remains at approximately 1.6 V, regardless of the state of

Bit DB5 and Bit DB4 in Register 14.

+22dB

100Ω

EXTERNAL

CONTROL

PARALLEL

PORT

LATCH

CONTROL

LATCH

DGA

CONTROL

SELECT

VIN+

VIN–

VOUT+

VOUT–

ATTENUATOR

0dB TO 31.5dB

+22dB

300Ω

MUX

INTERNAL

CONTROL

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