Data Sheet

ADRF6658

Rev. A | Page 21 of 31

REGISTER 7

Control Bits

Program Register 7 by setting Bits[C4:C1] to 0111. Figure 34

shows the input data format for programming this register.

DGA Control Select

Bit DB22 selects the mode of control for the IF DGA. When this

bit is programmed to 0, the gain of each DGA block is set by

value of the relevant fields in Register 14: Bits[DB17:DB12] set

the DGA A gain for Channel A, and Bits[DB11:DB6] set the

DGA B gain for Channel B. When Bit DB22 in Register 7 is set

to 1, the gain is controlled by the external parallel ports: Pin A5

through Pin A0 for Channel A, and Pin B5 through Pin B0 for

Channel B.

Figure 34. Register 7 (R7)

RESERVED

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

0

0

0

0

CONTROL BITS

0

DCS

0

0

0

0

0

0

0

1

1

1

0

0

0

0

0

0

0

0

C3(1) C2(1) C1(1)

C4(0)

0

0

0

DCS

DGA CONTROL

SELECT

0

GAIN SET BY SPI REGISTER

1

GAIN SET BY EXTERNAL PINS