 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
EP1C3 Datasheet(PDF) 49 Page - Altera Corporation |
|
|
|||||||||||||||||||||||||||||
EP1C3 Datasheet(HTML) 49 Page - Altera Corporation |
|
|
49 / 94 page  Altera Corporation 49 Preliminary Information Cyclone FPGA Family Data Sheet Figure 31. Control Signal Selection per IOE In normal bidirectional operation, the designer can use the input register for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to- output performance. The OE register is available for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from the local interconnect in the associated LAB, dedicated I/O clocks, or the column and row interconnects. Figure 32 shows the IOE in bidirectional configuration. clk_out ce_in clk_in ce_out aclr/preset sclr/preset Dedicated I/O Clock [5..0] Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect oe io_coe io_caclr Local Interconnect io_csclr io_cce_out io_cce_in io_cclk |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
