of driving larger currents than the device can sustain without being damaged. It is important for the output power

of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the

Absolute Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs should be left disconnected.

8.2.3 Latching Logic

This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type

flip-flops, but include all logic circuits that act as volatile memory.

When the device is powered on, the state of each latch is unknown. There is no default state for each latch at

start-up.

The output state of each latching logic circuit only remains stable as long as power is applied to the device within

the supply voltage range specified in the Recommended Operating Conditions table.

8.2.4 Clamp Diode Structure

The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical

Placement of Clamping Diodes for Each Input and Output.

CAUTION

Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage

to the device. The input and output voltage ratings may be exceeded if the input and output clamp-

current ratings are observed.

GND

Logic

Input

Output

Device

Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output

8.3 Device Functional Modes

Function Table lists the functional modes of the SN74HCS595.

Table 8-1. Function Table

INPUTS

FUNCTION

SER

SRCLK

SRCLR

RCLK

OE

X

X

X

X

H

X

X

X

X

L

X

X

L

X

X

Shift register is cleared.

L

↑

H

X

X

First stage of the shift register goes low. Other stages store the data

of previous stage, respectively.

H

↑

H

X

X

First stage of the shift register goes high. Other stages store the data

of previous stage, respectively.

X

X

H

↑

X

Shift-register data is stored in the storage register.

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SN74HCS595

SCLS803B – OCTOBER 2020 – REVISED MAY 2021

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