8 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TLV360x comparators feature rail-to-rail inputs and outputs on supply voltages as low as 2.4 V. The LVDS

output stage is optimal for high speed applications that require low power consumption. The 1ns propagation

delay of the device makes it a suitable fit for applications involving optical reception, triggers for test and

measurement systems, and transceiver type applications that require a high speed signal to be carried over a

certain distance.

8.1.1 Adjustable Hysteresis

As a result of a comparator’s high open loop gain, there is a small band of input differential voltage where the

output can toggle back and forth between “logic high” and “logic low” states. This can cause design challenges

for inputs with slow rise and fall times or systems with excessive noise. These challenges can be overcome by

adding hysteresis to the comparator.

Since the TLV3604 does not have internal hysteresis, external hysteresis can be applied in the form of a positive

feedback loop that adjusts the trip point of the comparator depending on its current output state. See the Typical

Application section for more details. The TLV3605 on the other hand has a LE/HYST pin that can be used to

increase the internal hysteresis of the comparator. In order to change the internal hysteresis of the TLV3605,

connect a single resistor as shown in the adjusting hysteresis figure between the LE/HYST pin and VEE. A curve

of hysteresis versus resistance is provided below to provide guidance in setting the desired amount of hysteresis

8.1.2 Capacitive Loads

Under reasonable capacitive loads, the device maintains specified propagation delay (see Typical

Characteristics). However, excessive capacitive loading under high switching frequencies may increase supply

current, propagation delay, or induce decreased slew rate.

8.1.3 Latch Functionality

The latch pin for the TLV3603 holds the output state of the device when the voltage at the LEB/HYST pin is

less than 800mV above VEE. This is particularly useful when the output state is intended to remain unchanged.

An important consideration of the latch functionality is the latch hold and setup times. Latch hold time is the

minimum time (after the latch pin is asserted) required for properly latching the comparator output. Likewise,

latch setup time is defined as the time that the input must be stable before the latch pin is asserted low. The

figure below illustrates when the input can transition for a valid latch. Note that the typical setup time in the

EC table is negative; this is due to the internal trace delays of the LEB/HYST pin relative to the input pin trace

delays. A small delay in the output response is shown below when the TLV3603 exits a latched output stage.

TLV3601, TLV3603

SNOSDB1 – JUNE 2021

www.ti.com

8

Submit Document Feedback

Copyright © 2021 Texas Instruments Incorporated

Product Folder Links: TLV3601 TLV3603