MCP39F511N datasheet(7/61 Pages) MICROCHIP

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 2015-2018 Microchip Technology Inc.

DS20005473B-page 7

MCP39F511N

DVDD Rise Rate to

Ensure Internal

Power-on Reset Signal

SDVDD

0.05

—

V/ms

0 – 3.3V in 0.1s, 0 – 2.5V

in 60 ms

AVDD Start Voltage to

Ensure Internal

Power-on Reset Signal

VPOR

AGND

—2.1

AVDD Rise Rate to

Ensure Internal Power-on

Reset Signal

SAVDD

0.042

—

V/ms

0 – 2.4V in 50 ms

Operating Current

IDD

—15

—

Data EEPROM Memory

Cell Endurance

EPS

100,000

—

E/W

Self-Timed

Write Cycle Time

TIWD

—4

—

Number of Total

Write/Erase Cycles

Before Refresh

RREF

—

10,000,000

—E/W

Characteristic Retention

TRETDD

—

Years Provided no other

specifications are violated

Supply Current during

Programming

IDDPD

—7

—

TABLE 1-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AVDD, DVDD = 2.7 to 3.6V,

TA = -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1.

Characteristic

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Note 1:

Calculated from reading the register values with no averaging, single computation cycle with accumulation

interval of 16 line cycles, channel 1 or channel 2.

Specification by design and characterization; not production tested.

N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or

TCAL = 320 ms for 50 Hz line.

Applies to Voltage Sag and Voltage Surge events only.

Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical

Performance Curves” for typical performance.

VIN =1 VPP =353 mVRMS @50/60 Hz.

Variation applies to internal clock and UART only.

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