MCP47FVB01 datasheet(65/92 Pages) MICROCHIP

65 / 92 page

 2015 Microchip Technology Inc.

DS20005429B-page 65

MCP48FEBXX

7.3

Commands to Modify the Device

Configuration Bits

The MCP48FEBXX devices support two commands

which are used to program the device’s configuration

bits. These commands require a high voltage (VIHH) on

the HVC pin. These commands are:

• Enable Configuration Bit

• Disable Configuration Bit

The configuration bits are used to inhibit the DAC

values from inadvertent modification. High voltage is

required to change the state of these bits if/when the

DAC values need to be modified.

7.4

Enable Configuration Bit

(High Voltage)

Figure 7-11 (Enable) shows the formats for a single

Enable

Configuration

Bit

command. The

command will only start the EEPROM write cycle (tWC)

after a properly formatted command has been

received.

During an EEPROM write cycle, only serial commands

to volatile memory are accepted. All other serial

commands are ignored until the EEPROM write cycle

(tWC) completes. This allows the Host Controller to

operate on the volatile DAC, the volatile VREF,

Power-Down, Gain and Status, and WiperLock

Technology Status registers. The EEWA bit in the

Status register indicates the status of the EEPROM

write cycle.

7.4.1

HIGH-VOLTAGE COMMAND (HVC)

SIGNAL

The High-Voltage Command (HVC) signal is used to

indicate that the command, or sequence of commands,

are in the High-Voltage mode. Signals higher than VIHH

(~9.0V) on the LAT/HVC pin puts the device into

High-Voltage mode. High-Voltage commands allow the

device’s WiperLock technology and write-protect

features to be enabled and disabled.

FIGURE 7-11:

Enable Command Sequence.

Note 1:

There is a required delay after the

HVC pin is driven to the VIHH level on the

1st edge of the SCK pin.

1111111111111111 Valid

1111111

Invalid (1, 2)

SDI

SDO

Note 1:

If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid.

This command will not be completed and requires the CS pin to return to VIH to clear the

CMDERR condition.

Address

Command

MCP47FVB01 Datasheet(PDF) 65 Page - Microchip Technology

MCP47FVB01 Datasheet(HTML) 65 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL