MCP47FVB01 datasheet(67/92 Pages) MICROCHIP

67 / 92 page

 2015 Microchip Technology Inc.

DS20005429B-page 67

MCP48FEBXX

7.5

Disable Configuration Bit

(High Voltage)

Figure 7-14 (Disable) shows the formats for a single

Disable

Configuration

Bit

command. The

command will only start an EEPROM write cycle (tWC)

after a properly formatted command has been

received.

During an EEPROM write cycle, only serial commands

to volatile memory are accepted. All other serial

commands are ignored until the EEPROM write cycle

(tWC) completes. This allows the Host Controller to

operate on the volatile DAC, the volatile VREF,

Power-Down, Gain and Status, and WiperLock

Technology Status registers. The EEWA bit in the

Status register indicates the status of an EEPROM

write cycle.

7.5.1

HIGH-VOLTAGE COMMAND (HVC)

SIGNAL

The High-Voltage Command (HVC) signal is used to

indicate that the command, or sequence of commands,

are in the High-Voltage mode. Signals higher than VIHH

(~9.0V) on the HVC pin puts the MCP48FEBXX

devices into High-Voltage mode. High Voltage

commands allow the device’s WiperLock technology

and write protect features to be enabled and disabled.

FIGURE 7-14:

Disable Command Sequence.

Note 1:

There is a required delay after the HVC

pin is driven to the VIHH level to the 1st

edge of the SCK pin.

1111111111111111 Valid

1111111

Invalid (1, 2)

Address

SDI

SDO

Command

Note 1:

If an Error condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid.

This command will not be completed and requires the CS pin to return to VIH to clear the

CMDERR condition.

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