8 Detailed Description

8.1 Overview

The SN74HCS594-Q1 is an 8-bit shift register that feeds an 8-bit D-type storage register. Both the shift register

clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected

together, the shift register always is one clock pulse ahead of the storage register. All inputs include Schmitt-

triggers allowing for slow input transitions and providing more noise margin.

8.2 Functional Block Diagram

RCL K

RCL R

SRCLR

SRCLK

SER

13

12

10

11

14

D

R

15

1

Q

D

R

Q

D

Q

D

Q

2

3

4

5

6

D

R

7

9

Q

D

Q

R

R

R

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS594

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important for the output power

of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the

Absolute Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs should be left disconnected.

8.3.2 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are

typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table

from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the

Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics

table, using Ohm's law (R = V ÷ I).

SN74HCS594

SCLS839A – OCTOBER 2020 – REVISED MAY 2021

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