PLL205-01
Motherboard Clock Generator for AMD - K7
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/07/00 Page 2
PIN DESCRIPTIONS
Name
Number
Type
Description
VDD0
1
P
Power supply for PLL CORE.
VDD1
6
P
Power supply for REF0, REF1, and crystal oscillator.
VDD2
14
P
Power supply for PCI (0:5).
VDD3
19,30,36,42
P
Power supply for SDRAM (0:12).
VDD4
27
P
Power supply for 24_48MHz and 48MHz.
GND
3,9,16,22,
33,39,45,47
P
Ground.
XIN
4
I
14.318MHz crystal input that has internal loads cap (36pF) and feedback
resistor from XOUT.
XOUT
5
O
14.318MHz crystal output. It has internal load cap (36pF).
REF0//CPU_STOP
2
B
Multiplexed pin controlled by MODE signal. When CPU_STOP is low, it
will halt CPUT (0:1), CPUC0 and SDRAM (0:11) outputs. In output
mode, this pin will generate buffered reference clock output.
PCI5/MODE
7
B
At power-up, MODE function will be activated. When MODE is Low, Pin
2 is input for CPU_STOP. When high, Pin 2 is output for REF0. After
input data latched, this pin will generate PCI bus clock.
PCI0/FS3
8
B
At power-up, this pin is input pin and will determine CPU clock
frequency. After input sampling, this pin will generate output clocks. FS3
has internal pull up (high by default).
PCI1/SEL24_48
10
B
At power-up, this pin will select 24MHz (when high) or 48MHz (when
low) for pin25 output. After input sampling, this pin is PCI output. It has
internal pull up resistor.
PCI(2:4)
11,12,13
O
PCI clock outputs.
SDRAMIN
15
I
Buffer input pin: The signal provided to this input pin is buffered to 13
SDRAM outputs.
SDRAM(0:11)
17,18,20,21,28,
29,31,32,34,35,
37,38
O
SDRAM clock outputs, Fan-out Buffer outputs from SDRAMIN pin.
SDATA
23
B
SCLK
24
I
Serial data inputs for serial interface port.
24_48MHz/FS1,
24MHz/FS0
25,26
B
At power-up, these pins are input pins and will determine the CPU clock
frequency. FS0, FS1 have internal pull up (high by default).
SDRAM12
40
O
When CPU_STOP is low, this pin is still free running. When the power
down is low, this SDRAM will be stopped.
PD#
41
I
When low, it will stop all clock outputs. It has internal pull-up resistor.
CPUT(0:1)
43,46
O
“True” clocks of differential pair open-drain CPU outputs.
CPUC0
44
O
“Complementary” clocks of differential pair open-drain CPU outputs.
REF1/FS2
48
B
Buffered reference clock output after input data latched during power-up.
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