PLL205-01XM datasheet(7/12 Pages) ETC1

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PLL205-01

Motherboard Clock Generator for AMD - K7

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 03/07/00 Page 7

8. BYTE 7: Linear Programming (M) Register (1=Enable, 0=Disable)

Bit

Pin#

Default

Description

Bit 7

Linear programming sign bit ( 0 is “

+”, 1 is “−” )

Bit 6

Linear programming magnitude bit 6 (MSB)

Bit 5

Linear programming magnitude bit 5

Bit 4

Linear programming magnitude bit 4

Bit 3

Linear programming magnitude bit 3

Bit 2

Linear programming magnitude bit 2

Bit 1

Linear programming magnitude bit 1

Bit 0

Linear programming magnitude bit 0 (LSB)

9. BYTE 8: Device ID Register (1=Enable, 0=Disable)

Bit

Pin#

Default

Description

Bit 7

Reserved

Bit 6

Device ID Bit 6*

Bit 5

Device ID Bit 5*

Bit 4

Device ID Bit 4*

Bit 3

Device ID Bit 3*

Bit 2

Device ID Bit 2*

Bit 1

Device ID Bit 1*

Bit 0

Device ID Bit 0*

Note: *: Default value at power-up

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