MICRF620TR datasheet(16/18 Pages) MICREL

16 / 18 page

Micrel, Inc.

MICRF620

December 2005

M9999-120205

A bit synchronizer can be enabled in receive mode by

selecting the synchronous mode (Sync_en=1). The

DataClk pin will output a clock with twice the frequency of

the bit rate (a bit rate of 20 kbit/sec gives a DataClk of 20

kHz). A received symbol/bit on DataIXO will be output on

rising edge of DataClk. The micro controller should

therefore sample the symbol/bit on falling edge of DataClk.

The bit synchronizer uses a clock that needs to be

programmed according to the bit rate. The clock frequency

should be 16 times the actual bit rate (a bit rate of 20

kbit/sec needs a bit synchronizer clock with frequency of

320 kHz). The clock frequency is set by the following

formula:

lkS)

-BITSYNC_c

XCO

BITSYNC_CL

Refclk_K

where

fBITSYNC_CLK: The bit synchronizer clock frequency

(16 times higher than the bit rate)

fXCO: Crystal oscillator frequency

Refclk_K: 6 bit divider, values between 1 and 63

BitSync_clkS: Bit synchronizer setting, values

between 0 and 7

Refclk_K is also used to derive the modulator clock and

the bit rate clock.

At the beginning of a received data package, the bit

synchronizer clock frequency is not synchronized to the bit

rate. When these two are maximum offset to each other, it

takes 22 bit/symbols before synchronization is achieved.

Transmitter

Power Amplifier

A6..A0

0000000

LNA_by

PA2

PA1

PA0

Sync_en

Mode1

Mode0

’1’

0000001

‘1’

‘0’

RSSI_en

LD_en

PF_FC1

PF_FC0

The maximum output power is approximately 10dBm for a

50Ω load. The output power is programmable in seven

steps, with approximately 3dB between each step. Bits

PA2 – PA0, control this. PA2 – PA0 = 1 give the maximum

output power.

The power amplifier can be turned off by setting PA2 –

PA0 = 0.

For all other combinations the PA is on and has maximum

power when PA2 – PA0 = 1.

Frequency Modulation

FSK modulation is applied by switching between two sets

of dividers (M,N,A). The formula for calculating the M, N

and A values is given in chapter Frequency synthesizer.

The divider values stored in the M0-, N0-, and A0-

registers will be used when transmitting a ‘0’ and the M1-,

N1-, and A1-registers will be used to transmit a ‘1’. The

difference

between

the

two

carrier

frequencies

corresponds to the double sided frequency deviation. The

data to be transmitted shall be applied to pin DataIXO (see

chapter Transceiver sync-/non-synchronous mode on how

to use the pin DataClk). The DataIXO pin is set as input in

transmit mode and output in receive mode.

Using the XCO-tune Bits

The module has a built-in mechanism for tuning the

frequency of the crystal oscillator and is often used in

combination with the Frequency Error Estimator (FEE).

The XCO tuning is designed to eliminate or reduce initial

frequency tolerance of the crystal and/or the frequency

stability over temperature.

A procedure for using the XCO tuning feature in

combination with the FEE is given below. The MICRF620

measures the frequency offset between the receivers LO

frequency and the frequency of the transmitter. The

receiver XCO frequency can be tuned until the receiver

and transmitter frequencies are equal.

A procedure like this can be called during production

(storing the calibrated XCO_tune value), at regular

intervals or implemented in the communication protocol

when the frequency has changed. The MICRF620

development system can test this feature.

Example: In FEE, count up+down pulses, counting 8 bits:

A perfect case ==> FEE = 0

If FEE > 0: LO is too low, increase LO by decreasing

XCO_tune value

v.v. for FEE < 0

FEE field holds a number in the range -128, … , 127.

However, it keeps counting above/below the range, which

is:

If FEE = -128 and still counting dwn-pulses:

1) =>-129 = +127

2) 126

3) 125

To avoid this situation, always make sure max count is

between limits.

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