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SH7706 Datasheet(PDF) 49 Page - Renesas Technology Corp |
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SH7706 Datasheet(HTML) 49 Page - Renesas Technology Corp |
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49 / 709 page  Rev. 4.00, 03/04, page 3 of 660 1.2 Block Diagram MMU TLB CPU UBC SCI TMU RTC SCIF ADC DAC AUD DMAC CMT I/O port External bus interface BSC CCN CACHE H-UDI INTC CPG/WDT Legend ADC AUD BSC CACHE CCN CMT CPG/WDT CPU DAC : A/D converter : Advanced user debugger : Bus state controller : Cache memory : Cache memory controller : Compare match timer : Clock pulse generator/watchdog timer : Central processing unit : D/A converter DMAC H-UDI INTC MMU RTC SCI SCIF TLB TMU UBC : Direct memory access controller : User debugging interface : Interrupt controller : Memory management unit : Realtime clock : Serial communication interface (with smart card interface) : Serial communication interface (with FIFO) : Address translation buffer : Timer unit : User break controller BRIDGE Figure 1.1 SH7706 Block Diagram |
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