SH7706 datasheet(13/709 Pages) RENESAS

13 / 709 page

Rev. 4.00, 03/04, page xiii of xlvi

Item

Page

Revision (See Manual for Details)

10.3 Clock Operating Modes 294

Description amended

Table 10.2 shows the relationship between the mode control pin

(MD2 to MD0) combinations and the clock operating modes. Table

10.3 shows the usable frequency ranges in the clock operating

modes and frequency ranges of the input clock (crystal oscillation).

Operation cannot be guaranteed if settings other than those listed in

table 10.3 are used.

297

Caution 4 amended

4. The frequency of the peripheral clock (P

φ):

• The frequency of the peripheral clock (Pφ) is the product of the

frequency of the CKIO pin, the frequency multiplication ratio of

PLL circuit 1, and the division ratio of divider 2.

Section 11 Watchdog Timer

(WDT)

Figure 11.1 Block Diagram of

the WDT

303

Figure 11.1 amended

WTCSR

Standby

control

Bus interface

WTCNT

Divider

Clock selector

Clock

Standby

mode

Peripheral

clock

Standby

cancellation

Reset

control

Clock selection

WDT

Overflow

Internal

reset

request

Interrupt

control

Interrupt

request

11.2.1 Watchdog Timer

Counter (WTCNT)

304

Description amended

… The WTCNT is initialized to H'00 only by a power-on reset through

the

RESETP pin. …

11.2.2 Watchdog Timer

Control/Status Register

(WTCSR)

304

Description amended

… The WTCSR is initialized to H'00 only by a power-on reset through

the

RESETP pin. …

12.5.2 Status Flag Clear

Timing

Figure 12.9 Status Flag

Clear Timing

323

Figure 12.9 amended

Peripheral address bus

UNF, ICPF

TCR address

TCR write cycle

13.3.9 Second Alarm

333

Bit 7 R/W amended

(Before) R

→ (After) R/W

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