Symbol

Parameter

Remark

Standard Mode*

±10%

Unit

Min.

Max.

Min.

Max.

Bus Free Time

Time in which the bus must

be free before a new trans-

mission can start

4700

¾

1200

¾

ns

Input Filter Time Constant

(SDA and SCL Pins)

Noise suppression time

¾

100

¾

50

ns

Write Cycle Time

¾¾

5

¾

5ms

Note:

These parameters are periodically sampled but not 100% tested

For relative timing, refer to timing diagrams

HT24LC64

Rev. 1.00

3

January 5, 2005

Functional Description

The SCL input is used for positive edge clock data into

each EEPROM device and negative edge clock data

out of each device.

The SDA pin is bidirectional for serial data transfer.

The pin is open drain driven and may be wired-OR

with any number of other open drain or open collector

devices.

The A2, A1 and A0 pins are device address inputs that

are hard wired or left not connected for hardware com-

patibility with HT24LC64. When the pins are hard-

wired, as many as eight 64K devices may be

addressed on a single bus system (device addressing

is discussed in detail under the Device Addressing

establish the device select code.

The HT24LC64 has a write protect pin that provides

hardware data protection. The write protect pin allows

normal read/write operations when the connection is

grounded. When the write protect pin is connected to

ates as shown in the following table.

WP Pin Status

Protect Array

Full Array (64K)

Normal Read/Write Operations

Memory Organization

Internally organized with 8192 8-bit words, the 64K re-

quires a 13-bit data word address for random word ad-

dressing.

Device Operations

Data transfer may be initiated only when the bus is not

busy. During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

data line while the clock line is high will be interpreted

as a START or STOP condition.

A high-to-low transition of SDA with SCL high is a start

condition which must precede any other command

(refer to Start and Stop Definition Timing diagram).

A low-to-high transition of SDA with SCL high is a stop

condition. After a read sequence, the stop command

will place the EEPROM in a standby power mode (re-

fer to Start and Stop Definition Timing Diagram).

All addresses and data words are serially transmitted

to and from the EEPROM in 8-bit words. The

EEPROM sends a zero to acknowledge that it has re-

ceived each word. This happens during the ninth clock

cycle.

Device Addressing

The 64K EEPROM devices require an 8-bit device ad-

dress word following a start condition to enable the chip

for a read or write operation. The device address word

consist of a mandatory one, zero sequence for the first

four most significant bits (refer to the diagram showing

the Device Address). This is common to all the

EEPROM device.

The 64K EEPROM uses the three device address bits

A2, A1, A0 to allow as many as eight devices on the

same bus. These bits must compare to their corre-

sponding hardwired input pins.

S C L

S D A

D a t a a l l o w e d

t o c h a n g e

A d d r e s s o r

a c k n o w l e d g e

v a l i d

S t o p

c o n d i t i o n

S t a r t

c o n d i t i o n

N o A C K

s t a t e