HT24LC64

Rev. 1.00

4

January 5, 2005

The 8th bit device address is the read/write operation

select bit. A read operation is initiated if this bit is high

and a write operation is initiated if this bit is low.

If the comparison of the device address succeed the

EEPROM will output a zero at ACK bit. If not, the chip will

return to a standby state.

Write Operations

A write operation requires an 8-bit data word address

following the device address word and acknowledg-

ment. Upon receipt of this address, the EEPROM will

again respond with a zero and then clock in the first

8-bit data word. After receiving the 8-bit data word, the

EEPROM will output a zero and the addressing de-

vice, such as a microcontroller, must terminate the

write sequence with a stop condition. At this time the

EEPROM enters an internally-timed write cycle to the

nonvolatile memory. All inputs are disabled during this

write cycle and EEPROM will not respond until the

write operation is completed (refer to Byte write tim-

ing).

The 64K EEPROM is capable of a 32-byte page write.

A page write is initiated in the same way as a byte

write, but the microcontroller does not send a stop

condition after the first data word is clocked in. In-

stead, after the EEPROM acknowledges the receipt of

the first data word, the microcontroller can transmit up

to 31 more data words. The EEPROM will respond

with a zero after each data word received. The

microcontroller must terminate the page write se-

quence with a stop condition (refer to Page write tim-

ing).

The data word address lower 5 bits are internally in-

cremented following the receipt of each data word.

The higher data word address bits are not incre-

mented, retaining the memory page row location.

When the word address, internally generated,

reaches the page boundary, the following byte is

placed at the beginning of the same page. If more

than 32 data words are transmitted to the EEPROM,

the data word address will

²roll over² and previous

data will be overwritten.

To maximize bus throughput, one technique is to allow

the master to poll for an acknowledge signal after the

start condition and the control byte for a write com-

mand have been sent. If the device is still busy imple-

menting its write cycle, then no ACK will be returned.

The master can send the next read/write command

when the ACK signal has finally been received.

R / W

1

0

A 2

A 1

A 0

D e v i c e A d d r e s s

1

0

Device Address

D e v i c e A d d r e s s

F i r s t W o r d A d d r e s s

S D A L i n e

A 2 A 1 A 0

S e c o n d W o r d A d d r e s s

D a t a

Byte Write Timing

D e v i c e A d d r e s s

F i r s t W o r d A d d r e s s ( n )

S D A L i n e

A 2 A 1 A 0

S e c o n d W o r d A d d r e s s ( n )

D a t a ( n + x )

D a t a ( n )

N o t e : * = D o n ' t c a r e b i t s

Page Write Timing

S e n d W r i t e C o m m a n d

S e n d S t o p C o n d i t i o n

t o I n i t i a t e W r i t e C y c l e

S e n d S t a r t

S e n d C o n t r o l B y t e

w i t h R / W = 0

( A C K = 0 ) ?

N e x t O p e r a t i o n

N o

Y e s

Acknowledge Polling Flow