8.4.2 OE[7:0]# and SMBus Output Enables

Each output channel, 0 to 7, can be individually enabled or disabled by a SMBus control register bit, called

SMB enable bits. Additionally, each output channel has a dedicated, corresponding, OE[7:0]# hardware pin. The

OE[7:0]# pins are asynchronously asserted-low signals that may enable or disable the output.

Refer to Table 8-1 for enabling and disabling outputs through the hardware and software. Note that both the

SMB enable bit must be a 1 and the OEx# pin must be an input low voltage 0 for the output channel to be active.

Table 8-1. OE[7:0]# Functionality

Control Inputs

Power State Variables

(Internal)

CLKIN

OE[7:0]# HARDWARE PINS AND SMBus

CONTROL REGISTER BITS

CK[7:0]_P/

CK[7:0]_N

CKPWRGD_P

D#

PWRGD

PD#

OE[7:0]#

OUT_EN_CLK[

7:0]

DRIVE_OP_ST

ATE_CTRL

0

0

0

X

X

X

X

LOW/LOW

1

1

1

X(1)

X

0

0

LOW/LOW

1

TRI-STATE

1

X

0

LOW/LOW

1

TRI-STATE

Running(1)

0

1

X

Running

0

0

X(2)

X

X

0

LOW/LOW

1

TRI-STATE

(1)

To enter the power-down state, CLKIN must remain active for at least 3 clock cycles after CKPWRGD_PD# transitions from 1 to 0.

(2)

To enter the powered-up state with active clock outputs, CLKIN must be active before CKPWRGD_PD# transitions from 0 to 1.

8.4.3 Output Slew Rate Control

The CDCDB800 provides output slew rate control feature which customer can use to compensate for increased

output trace length based on their board design. The slew rate of a bank of 4 outputs 0 to 3 and 4 to 7, can

be changed within a given range by a SMBus control register called CAPTRIM. Refer to Table 8-15 for more

information.

8.4.4 Output Impedance Control

The integrated termination on the CDCDB800 can be programmed either for 85 Ω or 100 Ω. This flexibility

ensures that the customer can use the same device across various applications irrespective of the characteristic

board impedance which is typically either 85 Ω or 100 Ω. This termination resistor can be changed for all the

outputs as whole using bit 5 of a register called OUTSET. Refer to Table 8-13 for more information.

8.5 Programming

The CDCDB800 uses SMBus to program the states of its eight output drivers. See SMBus for more information

on the SMBus programming, and Register Maps for information on the registers.

Table 8-2. Command Code Definition

BIT

DESCRIPTION

7

0 = Block Read or Block Write operation

1 = Byte Read or Byte Write operation

(6:0)

Register address for Byte operations, or starting register address for Block, operations

CDCDB800

SNAS818 – JULY 2021

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