OPA140AIDBVT datasheet(25/48 Pages) TI

25 / 48 page

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.

Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to

the analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current. For more detailed information, see

Circuit Board Layout Techniques.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed

to in parallel with the noisy trace.

• Place the external components as close to the device as possible. As illustrated in Figure 10-1, keeping RF

and RG close to the inverting input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

• For best performance, TI recommends cleaning the PCB following board assembly.

• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to

remove moisture introduced into the device packaging during the cleaning process. A low temperature, post

cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

10.2 Layout Example

±IN

+IN

V±

V+

OUTPUT

VS+

VS±

GND

Ground (GND) plane on another layer

VOUT

VIN

GND

Run the input traces

as far away from

the supply lines

as possible

Place components close

to device and to each

other to reduce parasitic

errors

Use low-ESR,

ceramic bypass

capacitor

GND

Use a low-ESR,

ceramic bypass

capacitor

Figure 10-1. Operational Amplifier Board Layout for Noninverting Configuration

www.ti.com

OPA140, OPA2140, OPA4140

SBOS498E – JULY 2010 – REVISED JULY 2021

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