SSD0817 Series
Rev 1.3
01/2003
SOLOMON
7
M
This pin is the frame signal input/output. In master mode, this pin supplies the frame signal to slave
devices. In slave mode, this pin receives the frame signal from the master device.
CL
This pin is the system clock input/output. When both the internal oscillator (CLS pin pulled high) and
the master mode (M/S pin pulled high) are enabled, the CL pin will supplies system clock signal to the
slave device. When both internal oscillator and the slave mode are enabled, the CL pin receives
system clock signal from either the master device or the external clock source.
DOF DOF
This pin is the display blanking signal control pin. In master mode, the
DOF pin supplies “display on”
or “display off” signal (blanking signal) to the slave devices. In slave mode, the DOF pin receives
“display on” or “display off” signal from the master device.
1
CS
, CS2
These pins are the chip selection inputs. The chip is enabled for MCU communication only
when
1
CS is pulled low and CS2 is pulled high.
RES RES
This pin is the reset signal input. Initialization of the chip is started once the reset pin is pulled low.
The minimum pulse width for completion of the reset procedure is 5 -10 us.
SA0, SCL, SDAout, SDAin
These pins are bi-directional data bus to be connected to the MCU in I
2C-bus interface. Please refer
to the section: I
2C Communication interface on page 11 for detail pin descriptions.
VDD
The VDD is the Chip’s Power Supply pins. VDD is also acted as a reference level of both the DC-DC
Converter and the LCD driving output.
VSS
The Vss is the grounding of the chip. Vss is also acted as a reference level of the logic input/output.
VSS1
The VSS1 is the input of the internal DC-DC converter. The generated voltage from the internal DC-DC
converter, VEE, is equal to the multiple factors (2X, 3X, 4X, 5X) times the potential different between
VSS1, and VDD. The multiple factors, 2X, 3X, 4X or 5X are selected by different arrangements of the
external boosting capacitors.
Note: the potential at this input pin must lower than or equal to VSS.
VEE
This is the most negative voltage supply pin of the chip. It can be supplied externally or generated by
the internal DC-DC converter. If the internal DC-DC converter generates the voltage level at VEE, the
voltage level is used for internal referencing only. The voltage level at VEE pins is not used for driving
external circuitry.
C1P, C1N, C2N, C2P C3N and C4N
When internal DC-DC voltage converter is used, external capacitor(s) is/are connected between these
pins. Different connections result in different DC-DC converter multiple factors, for example, 2X, 3X,
4X or 5X. Please refer to the voltage converter section in the functional block description for detail
description.
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