XRT83L34 datasheet(2/82 Pages) EXAR

2 / 82 page

XRT83L34

QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.3.4

FEATURES

• Fully integrated four channel long-haul or short-

haul transceivers for E1,T1 or J1 applications

• Adaptive Receive Equalizer for up to 36dB cable

attenuation

• Programable Transmit Pulse Shaper for E1,T1 or J1

short-haul interfaces

• Five fixed transmit pulse settings for T1 short-haul

applications plus a fully programmable waveform

generator for transmit output pulse shaping that

can be used for both T1 and E1 modes.

• Transmit Line Build-Outs (LBO) for T1 long-haul

application from 0dB to -22.5dB in three 7.5dB

steps

• Selectable receiver sensitivity from 0 to 36dB cable

loss for T1 @772kHz and 0 to 43dB for E1

@1024kHz

• Receive monitor mode handles 0 to 29dB resistive

attenuation along with 0 to 6dB of cable attenuation

for E1 and 0 to 3dB of cable attenuation for T1

modes

• Supports 75Ω and 120Ω (E1), 100Ω (T1) and 110Ω

(J1) applications

• Internal and/or external impedance matching for

Ω, 100Ω, 110Ω and 120Ω

• Tri-State transmit output and receive input

capability for redundancy applications

• Provides High Impedance for Tx and Rx during

power off

• Transmit return loss meets or exceeds ETSI 300-

166 standard

• On-chip digital clock recovery circuit for high input

jitter tolerance

• Crystal-less digital jitter attenuator with 32-bit or 64-

bit FIFO selectable either in transmit or receive path

• On-chip frequency multiplier generates T1 or E1

Master clocks from variety of external clock sources

• High receiver interference immunity

• On-chip transmit short-circuit protection and

limiting, and driver fail monitor output (DMO)

• Receive loss of signal (RLOS) output

• On-chip

HDB3/B8ZS/AMI

encoder/decoder

functions

• QRSS pattern generator and detection for testing

and monitoring

• Error and Bipolar Violation Insertion and Detection

FIGURE 2 BLOCK DIAGRAM OF THE XRT83L34 T1/E1/J1 LIU (HARDWARE MODE)

One of four Ch annels, C HAN NEL_n - (n=0 : 3)

HW /HO ST

GAUG E

JAS EL1

JAS EL0

RXT S EL

TXTS EL

TE RS EL1

TE RS EL0

RXRE S1

RXRE S0

IC T

MC LKE1

MCLKT1

CLKSE L[2:0]

T POS_n/TDA TA_n

TNEG _n/C OD ES_n

TC LK_n

RC LK_n

R NEG _n/LC V_n

RPO S_n/RDA TA_n

RLO S_n

RTIP_n

RRIN G_n

MAST ER CL OC K SYNT H ESIZER

QRSS

PAT T ERN

GENE RAT OR

DMO_n

TTIP_n

TRING_n

TXON_n

HDB3 /

B8Z S

EN CO DER

TX/RX JITT ER

AT T EN UAT OR

TIMING

CO NT R OL

TX FILTER

& PUL SE

SHAPER

LINE

D RIVER

LO CAL

AN AL OG

L OO PBACK

REMOT E

LO O PBACK

DIGIT AL

LOOPBACK

HDB3 /

B8Z S

D ECO DER

TX/RX JITT ER

AT T EN UAT OR

TIMIN G &

DAT A

REC OVER Y

PEAK

DET E CT O R

& SL ICER

QR SS

DET ECT O R

NET W O RK

LO OP

DET ECT O R

EQ UALIZ ER

CO NT R OL

AIS

DET ECT O R

LO S

DET EC T OR

LBO [3:0]

L OO PBACK

ENAB LE

NL CD ENABL E

QR SS ENAB LE

HARW AR E C ON T RO L

T EST

RESE T

TRA T IO

SR/DR

EQ C[4:0]

TCLK E

RCLK E

RXMUT E

AT AO S

DR IVE

MO NIT O R

DF M

MCLKO UT

TAOS_n

LO OP 1_n

LO OP 0_n

XRT83L34 Datasheet(PDF) 2 Page - Exar Corporation

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