AT25FF321A datasheet(2/119 Pages) DIALOG

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Datasheet

2021-08-19

DS-AT25FF321A-181

Revision J

AT25FF321A

32-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory

with Multi-I/O Support

Contents

Features .................................................................................................................................................................................... 1

Contents.................................................................................................................................................................................... 2

Figures ...................................................................................................................................................................................... 8

Tables........................................................................................................................................................................................ 9

1 Product Overview ............................................................................................................................................................... 10

2 Block Diagram .................................................................................................................................................................... 11

3 Pin Descriptions ................................................................................................................................................................. 12

4 Device Operation ................................................................................................................................................................ 15

4.1 Data Transfer Modes ...............................................................................................................................................15

4.2 Standard SPI Operation ...........................................................................................................................................15

4.2.1 Command Only, No Address or Data (1-0-0) ............................................................................................. 16

4.2.2 Command and Address Only, No Data (1-1-0) .......................................................................................... 16

4.2.3 Command and Data Only, No Address (1-0-1) .......................................................................................... 17

4.2.4 Command, Address, and Data (1-1-1) ....................................................................................................... 18

4.3 Dual Output Operation (1-1-2) .................................................................................................................................19

4.4 Quad Output Operation (1-1-4) ................................................................................................................................20

4.5 Quad I/O Operation (1-4-4) ......................................................................................................................................21

4.6 XiP Mode Operation .................................................................................................................................................22

4.6.1 Initial Transfer and XiP Mode Detection (M[5:4]) ....................................................................................... 22

4.6.2 Subsequent Transfers ................................................................................................................................ 23

4.6.3 Set Burst with Wrap ................................................................................................................................... 24

4.7 Memory Architecture ................................................................................................................................................24

4.8 Memory Protection ...................................................................................................................................................27

4.8.1 Standard Memory Protection ..................................................................................................................... 27

4.8.2 Individual Block Lock and Unlock ............................................................................................................... 29

4.8.3 Global Block Lock and Unlock ................................................................................................................... 30

4.8.4 Reading the State of the Lock Bits ............................................................................................................. 30

4.9 Power Down Considerations ....................................................................................................................................30

4.9.1 Entering Power Down Mode ...................................................................................................................... 31

4.9.2 Exiting Power Down Mode ......................................................................................................................... 31

4.9.3 ABh Command ........................................................................................................................................... 31

4.9.4 Device Resets ............................................................................................................................................ 31

4.9.5 Enable Reset (66h) / Reset (99h) Command ............................................................................................. 31

4.9.6 Terminate Command (F0h) ........................................................................................................................ 32

4.9.7 Reset During Program and Erase Commands ........................................................................................... 32

4.10 Erase/Program Suspend Considerations and Nested Operations .........................................................................33

4.10.1 Nested Operations ................................................................................................................................... 33

4.10.2 Suspending and Terminating a Program or Erase Operation ................................................................. 35

4.10.3 Terminating a Non-Volatile Operation in Progress ................................................................................... 35

4.11 OTP Security Register Lock ...................................................................................................................................36

4.12 Standard JEDEC Hardware Reset .........................................................................................................................36

4.13 Chip Select Restrictions .........................................................................................................................................37

4.14 HOLD / RESET Function .......................................................................................................................................37

5 Status Registers ................................................................................................................................................................. 39

5.1 Register Structure and Updates ...............................................................................................................................39

5.2 Register Accesses ...................................................................................................................................................40

5.2.1 Direct and Indirect Addressing ................................................................................................................... 40

5.2.2 Volatile and Non-Volatile Register Accesses ............................................................................................. 40

5.3 Status Register 1 .....................................................................................................................................................41

5.4 Status Register 2 .....................................................................................................................................................42

5.5 Status Register 3 .....................................................................................................................................................45

5.6 Status Register 4 .....................................................................................................................................................46

5.7 Status Register 5 ....................................................................................................................................................47

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