1.

Overview

The ATMX150RHA Design Manual, available from your Microchip technical center, provides the information and

flows necessary to design a mixed-signal ASIC for space applications. Users can be trained on Microchip-specific or

standard commercial tool kits and methodological details for actual implementations.

This offering is CMOS-technology-based, specified with 5/3.3/2.5V and HV 25-45V ranges for the periphery. Core is

supplied at 1.8V.

ATMX150RHA is manufactured on a 150nm, five-metal-layers SOI CMOS with Thick Metal technology option -

AT77KRHA, a Microchip proprietary process. The digital ATMX150RHA is qualified under the QML-V, QML-Q, and

ESCC QML. The domain of qualification covers the main features as follows.

• Comprehensive library of standard logic and I/O cells

• Memory Cells Compiled (ROM, SRAM, DPRAM, and Register File Memory)

• 450 MHz PLL (PLL400MRHA)

• Up to 22 usable Mgates (equivalent NAND2)

• Operating voltage 1.8±0.15V for the core and 5V±0.5V, 3.3±0.3V, 2.5±0.2V for the periphery

• High-speed LVDS buffers 655 Mbps in compliance with the TIA/EIA-644-A standard

• PCI buffers

• Set of analog blocks

• SEU-hardened flip-flops

• TID test up to 150 krads (Si) for 1.8V and 3.3V devices, and 90 krads (Si) for 5V according to MIL-STD 883

TM1019

• CCGA, CLGA, and CQFP qualified package catalog

ATMX150RHA

Overview

Datasheet

DS60001543C-page 4