3.

Core

3.1

Standard Cell Library

The Microchip Standard Cell Library contains a comprehensive set of logic and storage cells, including cells that

belong to the following categories:

• Buffers and gates

• Standard and SEU-hardened flip-flops

• Standard and SEU-hardened scan flip-flops

• Latches

• Multiplexers, adders, subtractors

3.2

Memory Hard Blocks

The ATMX150RHA memory libraries are developed from Virage memory compilers. All these memories are

synchronous. Four types of memories can be generated on request:

• Single-port synchronous SRAM

• Dual-port memory with two-port read/write synchronous SRAM

• Two-port synchronous register file with one read port and one write port

• ROM with metal programming

For maximum block sizes, refer to ATMX150RHA Design Manual, available from your Microchip technical center.

3.3

Analog Blocks

MICROCHIP proposes a catalog of analog IPs qualified that can be delivered with a datasheet and qualpack.

The qualification includes:

• Electrical characterization

• TID and SEE characterization

• HTOL tests

The analog IPs consist of Voltage regulators, a voltage reference and monitoring device, clock synthesizer and signal

conditioning IPs.

For more information on a complete list of available analog blocks, please contact the Microchip technical support

team in your region.

The following table lists the preliminary IP blocks and their features.

Table 3-1. Analog Blocks Catalog

IP Block

Features

PLL400MRHA

40-450 MHz PLL

ADC12RHA

12-bit 1 Msps ADC

DAC12RHA

12-bit 1 Msps DAC

MUX8RHA

8-channel analog multiplexer, 10 MHz bandwidth

OSCRC10MRHA

Programmable 4/8/10/12 MHZ RC oscillator, ±1% frequency variation over temperature

OSCRC32KRHA

32 kHz RC oscillator

BG1V2RHA

1.215V bandgap voltage reference, max temp. coef 90 ppm/°C

ATMX150RHA

Core

Datasheet

DS60001543C-page 6