Preliminary

PLL520-30

PECL and LVDS Low Phase Noise VCXO (for 65-130MHz Fund Xtal)

FEATURES

• 65MHz to 130MHz Fundamental Mode Crystal.

• Output range: 65MHz – 130MHz (no PLL).

• Low Injection Power for crystal 50uW.

• Complementary outputs: PECL or LVDS.

• Selectable OE Logic

• Integrated variable capacitors.

• Supports 2.5V or 3.3V-Power Supply.

• Available in die form.

• Thickness 10 mil.

DESCRIPTIONS

PLL520-30 is a VCXO IC specifically designed to

pull frequency fundamental crystals from 65MHz to

130MHz, with selectable PECL or LVDS outputs and

OE logic (enable high or enable low). Its design was

optimized to tolerate higher limits of interelectrodes

capacitance and bonding capacitance to improve

yield. It achieves very low current into the crystal

resulting in better overall stability. Its internal

varicaps allow an on chip frequency pulling,

controlled by the VCON input.

BLOCK DIAGRAM

DIE CONFIGURATION

Y

18

19

20

21

23

25

7

13

10

26

29

31

X

(0,0)

(1550,1475)

65 mil

24

22

17

16

15

14

12

11

9

8

6

1

2

3

45

27

28

30

DIE SPECIFICATIONS

Name

Value

Size

62 x 65 mil

Reverse side

GND

Pad dimensions

80 micron x 80 micron

Thickness

10 mil

OUTPUT SELECTION AND ENABLE

Pad #9

OUTSEL

Selected Output

0

LVDS

1

PECL (default)

X+

X-

OE

Q

PLL520-30

VCON

Q

Oscillator

Amplifier

w/

integrated

varicaps

Pad #25

OESEL

Pad #30

OE_CTRL

State

0

Tri-state

0

1

Output enabled (default)

0

Output enabled (default)

1

(default)

1

Tri-state

Pad #9, #25 and #30: Bond to GND to set to “0”, bond to VDD to set to “1”

Pad #30: Logical states defined by PECL levels if OESEL is “1”

Logical states defined by CMOS levels if OESEL is “0”

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 4/20/04 Page 1