AT25SF321B datasheet(49/61 Pages) DIALOG

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AT25SF321B

DS-AT25SF321B–179E–06-2020

12.6.1 Resume from Deep Power-Down and Read Device ID (ABh)

The Resume from Deep Power-Down command also can be used to read the Device ID.

When used to release the device from the Power-Down state and obtain the Device ID, the CS pin must first be

asserted and opcode ABh must be clocked into the device, followed by three dummy bytes. The Device ID bits are

then shifted out on the falling edge of SCLK with the MSB first, as shown in Figure 12-7. This command only

outputs a single byte Device ID. The Device ID value for the AT25SF321B is listed in Table 12-1 on page 41.

After the last bit (0) of the Device ID has been clocked out, the sequence repeats itself, starting again with bit 7, as

long as the CS pin remains asserted and the SCK pin is being pulsed. After CS is deasserted, it must remain high

until new commands can be received.

The same instruction can be used to read the device ID when not in power down mode. In that case, CS does not

have to remain high remain after it is deasserted.

Figure 12-7. Resume from Deep Power-Down and Read Device ID Timing

12.7 Hold Function

The HOLD pin pauses the serial communication with the device without having to stop or reset the clock sequence.

This mode does not affect internally self-timed operations, such as a program or erase cycle. Thus, if an erase

cycle is in progress, asserting the HOLD pin does not pause the operation, and the erase cycle continues until it is

finished.

If the QE bit value in the Status Register has been set to 1, the HOLD pin does not function as a control pin. The

HOLD pin functions as an output for Quad-Output Read and input/output for Quad-I/O Read.

The Hold mode can only be entered while the CS pin is asserted. This mode is activated by asserting the HOLD

pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, the Hold mode is not started

until the beginning of the next SCK low pulse. The device remains in this mode as long as the HOLD pin and CS

pin are asserted.

While in the Hold mode, the SO pin is in a high-impedance state. Also, both the SI pin and the SCK pin are ignored.

The WP pin, however, can be asserted or deasserted while in the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low

pulse. If the HOLD pin is deasserted during the SCK high pulse, the Hold mode does not end until the beginning of

the next SCK low pulse.

If the CS pin is deasserted while the HOLD pin is asserted, any operations that have been started are aborted, and

the device resets the WEL bit in the Status Register to 0.

SCK

MSB

ICC

10101011

OPCODE

HIGH-IMPEDANCE

Deep Power-Down Mode Current

Active Current

31 32

38 39

35 36

XXX

3 DUMMY BYTES

RDPO

MSB

DDDD

DEVICE ID

Standby Mode Current

AT25SF321B Datasheet(PDF) 49 Page - Dialog Semiconductor

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