AT25SL641 datasheet(31/76 Pages) DIALOG

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AT25SL641

DS-25SL641–113F–12/2018

Fast Read Quad I/O in QPI Mode

When QPI mode in enabled, the number of dummy clocks is configured by the Set Read Parameters (C0h) instruction to

accommodate a wide range applications with different needs for either maximum fast read frequency or minimum data

access latency. The number of dummy clock cycles can be configured as either 4, 6 or 8 by setting bits P[5:4] in the 8-

bit parameter of the Set Read Parameters (C0h) command as shown in Table 7-6, Encoding of P[5:4] Bits. The default

number of dummy clocks upon power up or after a Reset (99h) instruction is four.

The Continuous Read Mode feature is also available in QPI mode for Fast Read Quad I/O instruction. In QPI mode, the

Continuous Read Mode bits M7-M0 are also considered as dummy clocks.

The Wrap Around feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read operation

with fixed data length wrap around in QPI mode, a Burst Read with Wrap (0Ch) instruction must be used. Please refer to

Section 7.33, Burst Read with Wrap.

Figure 7-20. Fast Read Quad I/O Instruction (Initial instruction or previous M7-0 ≠ Axh, QPI mode)

7.15

Page Program (02h)

The Page Program instruction is used for programming the memory to “0”. A Write Enable instruction (06h) must be

issued before the device accept the Page Program Instruction (Status Register bit WEL = 1). After the Write Enable

(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) bit in the Status Register. The

instruction is entered by driving the CS pin low and then sending the instruction code 02h followed by a 24-bits address

(A23-A0) and at least one data byte on the SI pin. The CS pin must be driven low for the entire time of the instruction

while data is being sent to the device. The CS pin must be driven low for the entire time of the instruction while data is

being sent to the device. Please refer to Figure 7-21 and Figure 7-22.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set

to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing

wraps to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without

having any effect on other bytes within the same page. One condition to perform a partial page program is that the

number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing

wraps to the beginning of the page and overwrite previously sent data.

The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page

Program instruction is not executed. After CS is driven high, the self-timed Page Program instruction commences for a

time duration of tPP (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register

instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program

n+1

n+2 n+3 n+4

AT25SL641 Datasheet(PDF) 31 Page - Dialog Semiconductor