SLG46880 datasheet(3/353 Pages) DIALOG

3 / 353 page

Datasheet

25-Feb-2021

CFR0011-120-00

Revision 3.12

3 of 353

SLG46880/81

GreenPAK Programmable Mixed-Signal Matrix with Asynchronous

State Machine and Dual Supply

10.1 Deglitch Filter/Edge Detector ........................................................................................................................... 105

11 Voltage Reference .......................................................................................................................................................... 106

11.1 Voltage Reference Overview ........................................................................................................................... 106

11.2 Vref Selection Table ........................................................................................................................................ 106

11.3 Truth Table for Vref0 Buffer and Output Switch Control ..................................................................................107

11.4 Truth Table for Vref1 Buffer and Output Switch Control ..................................................................................107

11.5 Vref Block Diagram ......................................................................................................................................... 108

11.6 Vref Load Regulation ....................................................................................................................................... 109

12 Clocking .......................................................................................................................................................................... 111

12.1 General Description ......................................................................................................................................... 111

12.2 Oscillator0 (2.048 kHz) .....................................................................................................................................112

12.3 Oscillator1 (2.048 MHz) ................................................................................................................................... 113

12.4 Oscillator2 (25 MHz) ........................................................................................................................................ 114

12.5 Clock Scheme .................................................................................................................................................. 114

12.6 Crystal Oscillator .............................................................................................................................................. 116

12.7 External Clocking ............................................................................................................................................. 116

12.8 Oscillators Power-On Delay ............................................................................................................................. 117

12.9 Oscillators Accuracy ......................................................................................................................................... 119

13 Power-On Reset .............................................................................................................................................................. 122

13.1 General Operation ............................................................................................................................................ 122

13.2 POR Sequence ................................................................................................................................................123

13.3 Macrocells Output States During POR Sequence ........................................................................................... 123

14 Asynchronous State Machine Subsystem ................................................................................................................... 126

14.1 ASM Subsystem Overview ...............................................................................................................................126

14.2 ASM Subsystem Input Signals ......................................................................................................................... 128

14.3 ASM Subsystem Output Signals ...................................................................................................................... 131

14.4 Basic ASM_Subsystem Timing ........................................................................................................................ 133

14.5 ASM Power Considerations ............................................................................................................................. 134

14.6 Asynchronous State Machines vs. Synchronous State Machines ................................................................... 135

14.7 ASM Special Case Timing Considerations ...................................................................................................... 135

15 Asynchronous State Machine Macrocell ..................................................................................................................... 141

15.1 Asynchronous State Machine Overview .......................................................................................................... 141

15.2 ASM Macrocell Input Signals ........................................................................................................................... 142

15.3 ASM Logical vs. Physical Design ..................................................................................................................... 145

16 Dynamic Memory Macrocell ..........................................................................................................................................147

16.1 Dynamic Memory Macrocell Overview ............................................................................................................. 147

16.2 DM0_0 and DM0_1 Macrocell Architecture ..................................................................................................... 148

16.3 DM1_0 and DM1_1 Macrocell Architecture ..................................................................................................... 149

16.4 DMx_x Macrocell Input Signals ........................................................................................................................ 150

16.5 DMx_x Macrocell Output Signals ..................................................................................................................... 152

17 f(1) Computation Macrocell ........................................................................................................................................... 154

17.1 f(1) Computation Macrocell Overview ..............................................................................................................154

17.2 f(1) Computation Macrocell Architecture .........................................................................................................155

17.3 f(1) Computation Macrocell Input Signals ........................................................................................................ 155

17.4 f(1) Computation Macrocell Output Signals ..................................................................................................... 157

17.5 f(1) Command Registers .................................................................................................................................. 157

17.6 f(1) Typical Performance .................................................................................................................................. 164

18 Matrix Interface Macrocells ........................................................................................................................................... 165

18.1 MI0, MI1, and MI2 Macrocell Architecture ........................................................................................................ 165

18.2 MIx Macrocell Input Signals ............................................................................................................................. 166

18.3 MIx Macrocell Output Signals .......................................................................................................................... 166

19 I2C Serial Communications Macrocell .......................................................................................................................... 167

19.1 I2C Serial Communications Macrocell Overview .............................................................................................. 167

19.2 I2C Serial Communications Device Addressing ............................................................................................... 167

19.3 I2C Serial General Timing ................................................................................................................................ 168

19.4 I2C Serial Communications Commands ........................................................................................................... 168

19.5 I2C Serial Command Register Map .................................................................................................................. 172

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