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MPC866 Datasheet(PDF) 42 Page - NXP Semiconductors |
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MPC866 Datasheet(HTML) 42 Page - NXP Semiconductors |
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42 / 96 page  MPC866/MPC859 Hardware Specifications, Rev. 2 42 Freescale Semiconductor Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC866/859. Figure 30 shows the PCMCIA output port timing for the MPC866/859. Figure 30. PCMCIA Output Port Timing Figure 31 shows the PCMCIA output port timing for the MPC866/859. Figure 31. PCMCIA Input Port Timing Table 12. PCMCIA Port Timing Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit Min Max Min Max Min Max Min Max P57 CLKOUT to OPx, valid (MAX = 0.00 x B1 + 19.00) — 19.00 — 19.00 — 19.00 — 19.00 ns P58 HRESET negated to OPx drive 1(MIN = 0.75 x B1 + 3.00) 1 OP2 and OP3 only. 25.70 — 21.70 — 18.00 — 14.40 — ns P59 IP_Xx valid to CLKOUT rising edge (MIN = 0.00 x B1 + 5.00) 5.00 — 5.00 — 5.00 — 5.00 — ns P60 CLKOUT rising edge to IP_Xx invalid (MIN = 0.00 x B1 + 1.00) 1.00 — 1.00 — 1.00 — 1.00 — ns CLKOUT HRESET Output Signals OP2, OP3 P57 P58 CLKOUT Input Signals P59 P60 |
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