PECL Input OSCaR™ User Configurable Clock

MDS 525-03 H

2

Revision 010906

Integrated Circuit Systems, Inc.

ICS525-03

Pin Assignment

RES Value Table

Output Divider and Maximum Output Frequency Table

Note: 0 = connect directly to ground; 1 = connect directly to VDD.

18

7

17

8

16

9

15

PECL

10

11

GND

12

CLK1

13

V0

14

V1

GND

RES

V8

V2

V7

V5

V3

V6

22

21

20

19

V4

CLK2

5

6

S2

VDD

VDD

24

23

R0

3

4

S0

S1

R1

26

25

R2

1

2

R5

R6

R3

28

27

R4

28-pin SSOP

PECLIN

RES

CLK1

CLK2

Pre-divide (P)

0

CMOS

CMOS

2

1.1 k

Ω Resistor

to VDD

PECL

PECL

1

S0

S1

S2

CLK

Max. Output Frequency (MHz)

pin 5

pin 4

pin 3

Output Divider

(OD)

VDD = 5 V

VDD = 3.3 V

RES = 0

RES = 1.1 k

Ω

RES = 0

RES = 1.1 k

Ω

0

0

0

6

67

34

40

20

0

0

1

2

200

100

120

60

0

1

0

8

50

25

30

15

0

1

1

4

100

50

60

30

1

0

0

5

80

40

48

24

1

0

1

7

57

29

34

17

1

1

0

1

250

200

200

125

1

1

1

3

133

80

80

40