PECL Input OSCaR™ User Configurable Clock

MDS 525-03 H

3

Revision 010906

Integrated Circuit Systems, Inc.

ICS525-03

Pin Descriptions

KEY: I(PU) = Input with internal pull-up resistor.

Output Clock Selection

If RES is connected directly to ground, CLK1 and CLK2 are low skew, CMOS outputs clocks. They are not

complementary. If RES is connected to VDD through a 1.1 k

Ω resistor, then CLK1 and CLK2 become

complementary PECL outputs which require the external resistor network shown in the the block diagram. Refer to

Application Note MAN09 for additional information.

Pin

Number

Pin

Name

Pin

Type

Pin Description

1, 2,

24-28

R5, R6,

R0-R4

I(PU)

Reference divider word input pins determined by user. Forms a binary

number from 0 to 127.

3, 4, 5

S0, S1, S2

I(PU)

Select pins for output divider determined by user. See table above.

6, 23

VDD

Power

Connect to VDD.

7

PECLIN

Input

PECL input.

8

PECLIN

Input

Complementary PECL input.

9, 20

GND

Power

Connect to ground.

10 - 18

V0 - V8

I(PU)

VCO divider word input pins determined by user. Forms a binary number from

0 to 511.

19

RES

Input

Select eithe PECL or CMOS outputs. See table above.

21

CLK1

Output

Output clock. Either PECL or CMOS determined by RES.

22

CLK2

Output

Output clock. Either PECL or CMOS determined by RES.