AM79C978AVCW datasheet(123/256 Pages) AMD

123 / 256 page

Am79C978A

123

These bit are read/write accessi-

ble only when either the STOP or

the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR11: Logical Address Filter 3

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0 LADRF[63:48]Logical

Address

Filter,

LADRF[63:48]. The content of

this register is undefined until

loaded

from

the

initialization

block after the INIT bit in CSR0

has been set or a direct register

write has been performed on this

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR12: Physical Address Register 0

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PADR[15:0] Physical

Address

PADR[15:0]. The contents of this

EEPROM after H_RESET or by

an EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the

contents of this register are un-

defined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR13: Physical Address Register 1

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PADR[31:16]Physical

Address

PADR[31:16]. The contents of

this register are loaded from the

EEPROM after H_RESET or by

an EEPROM read command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the

contents of this register are un-

defined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

These bits are read/write acces-

sible only when either the STOP

or the SPND bit is set. These bits

are unaffected by H_RESET,

S_RESET, or STOP.

CSR14: Physical Address Register 2

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PADR[47:32]Physical

Address

PADR[47:32]. The contents of

this register are loaded from

the EEPROM after H_RESET

or by an EEPROM read com-

mand (PRGAD, BCR19, bit 14).

If the EEPROM is not present,

the contents of this register are

undefined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

AM79C978AVCW Datasheet(PDF) 123 Page - Advanced Micro Devices

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