AM79C978AVCW datasheet(119/256 Pages) AMD

119 / 256 page

Am79C978A

119

ble. As long as the Am79C978A

controller is not reset while in

suspend mode (by H_RESET,

S_RESET, or by setting the

STOP bit), no re-initialization of

the device is required after the

device comes out of suspend

mode. The Am79C978A control-

ler will continue at the transmit

and receive descriptor ring loca-

tions from where it had left, when

it entered the suspend mode.

This bit is always read/write ac-

cessible. SPND is cleared by

H_RESET,

S_RESET,

setting the STOP bit.

CSR6: RX/TX Descriptor Table Length

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-12

TLEN

Contains a copy of the transmit

encoded ring length (TLEN) field

read from the initialization block

during the Am79C978A control-

ler initialization. This field is writ-

ten

during

the

Am79C978A

initialization routine.

Read accessible only when ei-

ther the STOP or the SPND bit is

set. Write operations have no ef-

fect and should not be per-

formed. TLEN is only defined

after initialization. These bits are

unaffected

H_RESET,

S_RESET, or STOP.

11-8

RLEN

Contains a copy of the receive

encoded ring length (RLEN) read

from the initialization block during

Am79C978A controller initializa-

tion. This field is written during

the

Am79C978A

initialization

routine.

Read accessible only when ei-

ther the STOP or the SPND bit is

set. Write operations have no ef-

fect and should not be per-

formed. RLEN is only defined

after initialization. These bits are

unaffected

H_RESET,

S_RESET, or STOP.

7-0

RES

Reserved locations. Read as 0s.

Write operations are ignored.

CSR7: Extended Control and Interrupt 2

Certain bits in CSR7 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR7 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

FASTSPNDE

Fast Suspend Enable. When

FASTSPNDE is set to 1, the

Am79C978A controller performs

a fast suspend whenever the

SPND bit is set.

When a fast suspend is request-

ed, the Am79C978A controller

performs a quick entry into the

suspend mode. At the time the

SPND bit is set, the Am79C978A

controller will complete the DMA

process of any transmit and/or

receive packet that had already

begun DMA activity. In addition,

any transmit packet that had

started transmission will be fully

transmitted, and any receive

packet that had begun reception

will be fully received. However,

no additional packets will be

transmitted or received and no

additional transmit or receive

DMA activity will begin. Hence,

the Am79C978A controller may

enter the suspend mode with

transmit and/or receive packets

still in the FIFOs or the SRAM.

When FASTSPNDE is 0 and the

SPND bit is set, the Am79C978A

controller may take longer before

entering the suspend mode. At

the time the SPND bit is set, the

Am79C978A controller will com-

plete the DMA process of a trans-

mit packet if it had already begun,

and the Am79C978A controller

will completely receive a receive

packet if it had already begun.

Additionally, all transmit packets

stored in the transmit FIFOs and

the transmit buffer area in the

AM79C978AVCW Datasheet(PDF) 119 Page - Advanced Micro Devices

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