AM79C978AVCW datasheet(116/256 Pages) AMD

116 / 256 page

116

Am79C978A

by H_RESET or S_RESET and is

unaffected by the STOP bit.

MFCO

Missed Frame Counter Overflow is

set by the Am79C978A controller

when the Missed Frame Counter

(CSR112

and

CSR113)

has

wrapped around.

When MFCO is set, INTA is as-

serted if IENA is 1 and the mask

bit MFCOM is 0.

This bit is always read/write ac-

cessible. MFCO is cleared by the

host by writing a 1. Writing a 0

has no effect. MFCO is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

MFCOM

Missed Frame Counter Overflow

Mask. If MFCOM is set, the MFCO

bit will be masked and unable to

set the INTR bit.

This bit is always read/write ac-

cessible. MFCOM is set to 1 by

H_RESET or S_RESET and is

not affected by the STOP bit.

UINTCMD

User

Interrupt

Command.

UINTCMD can be used by the

host to generate an interrupt un-

related to any network activity.

When UINTCMD is set, INTA is

asserted if IENA is set to 1. Write

a 1 to UINT to clear UINTCMD

and stop interrupts.

This bit is always read/write ac-

cessible. UINTCMD is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

UINT

User Interrupt. UINT is set by the

Am79C978A controller after the

host has issued a user interrupt

command by setting UINTCMD

(CSR4, bit 7) to 1.

This bit is always read/write ac-

cessible. UINT is cleared by the

host by writing a 1. Writing a 0

has no effect. UINT is cleared by

H_RESET or S_RESET or by

setting the STOP bit.

RCVCCO

Receive Collision Counter Over-

flow is set by the Am79C978A

controller when the Receive Col-

lision

Counter

(CSR114

and

CSR115) has wrapped around.

When RCVCCO is set, INTA is

asserted if IENA is 1 and the

mask bit RCVCCOM is 0.

This bit is always read/write ac-

cessible. RCVCCO is cleared by

the host by writing a 1. Writing a

0 has no effect. RCVCCO is

cleared

H_RESET,

S_RESET, or by setting the

STOP bit.

RCVCCOM Receive Collision Counter Over-

flow Mask. If RCVCCOM is set,

the RCVCCO bit will be masked

and unable to set the INTR bit.

This bit is always read/write ac-

cessible. RCVCCOM is set to 1

by H_RESET or S_RESET and is

not affected by the STOP bit.

TXSTRT

Transmit Start status is set by the

Am79C978A controller whenever

it begins transmission of a frame.

When TXSTRT is set, INTA is as-

serted if IENA is 1 and the mask

bit TXSTRTM is 0.

This bit is always read/write ac-

cessible. TXSTRT is cleared by

the host by writing a 1. Writing a 0

has no effect. TXSTRT is cleared

by H_RESET, S_RESET, or by

setting the STOP bit.

TXSTRTM Transmit

Start

Mask.

TXSTRTM is set, the TXSTRT

bit will be masked and unable

to set the INTR bit.

This bit is always read/write ac-

cessible. TXSTRTM is set to 1

by H_RESET or S_RESET and

is not affected by the STOP bit.

1-0

RES

Reserved locations. Written as

zeros and read as undefined.

CSR5: Extended Control and Interrupt 1

Certain bits in CSR5 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

AM79C978AVCW Datasheet(PDF) 116 Page - Advanced Micro Devices

AM79C978AVCW Datasheet(HTML) 116 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL