AM79C978AVCW datasheet(114/256 Pages) AMD

114 / 256 page

114

Am79C978A

Note that because several de-

scriptors may be allocated by the

host for each packet, and not all

messages may need all of the de-

scriptors that are allocated be-

tween descriptors that contain

STP = 1, then some descriptors/

buffers may be skipped in the

ring. While performing the search

for the next STP bit that is set to

1, the Am79C978A controller will

advance through the receive de-

scriptor ring regardless of the

state of ownership bits. If any of

the entries that are examined

during

this

indicate

Am79C978A controller owner-

ship of the descriptor but also in-

dicate

STP = 0,

then

the

Am79C978A controller will reset

the OWN bit to 0 in these entries.

If a scanned entry indicates host

ownership with STP = 0, then the

Am79C978A controller will not al-

ter the entry, but will advance to

the next entry.

When the STP bit is found to be

true, but the descriptor that con-

tains this setting is not owned by

the Am79C978A controller, then

the Am79C978A controller will

stop advancing through the ring

entries and begin periodic polling

of this entry. When the STP bit is

found to be true, and the descrip-

tor that contains this setting is

owned by the Am79C978A con-

troller, then the controller will stop

advancing through the ring en-

tries, store the descriptor infor-

mation that it has just read, and

wait for the next receive to arrive.

This behavior allows the host

software

pre-assign

buffer

space in such a manner that the

header portion of a receive pack-

et will always be written to a par-

ticular memory area, and the data

portion of a receive packet will al-

ways be written to a separate

memory area. The interrupt is

generated when the header bytes

have been written to the header

memory area.

This bit is always read/write ac-

cessible. The LAPPEN bit will be

reset to 0 by H_RESET or

S_RESET and will be unaffected

by STOP.

See Appendix B for more infor-

mation on the Look Ahead Pack-

et Processing concept.

DXMT2PD

Disable Transmit Two Part Defer-

ral (see Medium Allocation sec-

tion

the

Media

Access

Management section for more

details). If DXMT2PD is set,

Transmit Two Part Deferral will

be disabled.

This bit is always read/write ac-

cessible. DXMT2PD is cleared by

H_RESET or S_RESET and is

not affected by STOP.

EMBA

Enable Modified Back-off Algo-

rithm (see the Contention Reso-

lution section in Media Access

Management section for more

details). If EMBA is set, a modi-

fied

back-off

algorithm

implemented.

This bit is always read/write ac-

cessible. EMBA is cleared by

H_RESET or S_RESET and is

not affected by STOP.

BSWP

Byte Swap. This bit is used to

choose between big and little

Endian

modes

operation.

When BSWP is set to a 1, big

Endian mode is selected. When

BSWP is set to 0, little Endian

mode is selected.

When big Endian mode is select-

ed, the Am79C978A controller will

swap the order of bytes on the AD

bus during a data phase on ac-

cesses to the FIFOs only. Specifi-

cally, AD[31:24] becomes Byte 0,

AD[23:16]

becomes

Byte

AD[15:8] becomes Byte 2, and

AD[7:0] becomes Byte 3 when big

Endian mode is selected. When

little Endian mode is selected, the

order of bytes on the AD bus dur-

ing a data phase is: AD[31:24] is

Byte 3, AD[23:16] is Byte 2,

AM79C978AVCW Datasheet(PDF) 114 Page - Advanced Micro Devices

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