AM79C978AVCW datasheet(121/256 Pages) AMD

121 / 256 page

Am79C978A

121

When MREINT is set to 1, INTA is

asserted

the

enable

bit

MREINTE is set to 1.

This bit is always read/write acces-

sible. MREINT is cleared by the

host by writing a 1. Writing a 0 has

no effect. MREINT is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP bit.

MREINTE

PHY Management Read Error In-

terrupt Enable. If MREINTE is

set, the MREINT bit will be able to

set the INTR bit.

This bit is always read/write ac-

cessible. MREINTE is set to 0 by

H_RESET and is not affected by

S_RESET or setting the STOP bit

MAPINT

PHY Management Auto-Poll In-

terrupt. The PHY Auto-Poll inter-

rupt is set by the Am79C978A

controller to indicate that the cur-

rently read status does not match

the stored previous status indi-

cating a change in state for the in-

ternal PHY. A change in the Auto-

Poll Access Method (BCR32, Bit

11) will reset the shadow register

and will not cause an interrupt on

the first access from the Auto-Poll

section. Subsequent accesses

will generate an interrupt if the

shadow register and the read

When MAPINT is set to 1, INTA is

asserted

the

enable

bit

MAPINTE is set to 1.

This bit is always read/write acces-

sible. MAPINT is cleared by the

host by writing a 1. Writing a 0 has

no effect. MAPINT is cleared by

H_RESET and is not affected by

S_RESET or setting the STOP bit.

MAPINTE

PHY Auto-Poll Interrupt Enable.

If MAPINTE is set, the MAPINT

bit will be able to set the INTR bit.

This bit is always read/write acces-

sible. MAPINTE is set to 0 by

H_RESET and is not affected by

S_RESET or setting the STOP bit.

MCCINT

PHY

Management

Command

Complete Interrupt. The PHY

Management Command Com-

plete Interrupt is set by the

Am79C978A controller when a

read or write operation to the in-

ternal PHY Data Port (BCR34) is

complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit

MCCINTE is set to 1.

This bit is always read/write ac-

cessible. MCCINT is cleared by

the host by writing a 1. Writing a

0 has no effect. MCCINT is

cleared by H_RESET and is not

affected by S_RESET or setting

the STOP bit.

MCCINTE

PHY

Management

Command

Complete Interrupt Enable. If

MCCINTE

set

the

MCCINT bit will be able to set the

INTR bit when the host reads or

writes to the internal PHY Data

Port (BCR34) only. Internal PHY

Management Commands will not

generate an interrupt. For in-

stance Auto-Poll state machine

generated management frames

will not generate an interrupt

upon completion unless there is a

compare error which gets report-

ed through the MAPINT (CSR7,

bit 6) interrupt or the MCCIINTE

is set to 1.

This bit is always read/write ac-

cessible. MCCINTE is set to 0 by

H_RESET and is not affected by

S_RESET or setting the STOP bit.

MCCIINT

PHY

Management

Command

Complete Internal Interrupt. The

PHY

Management

Command

Complete Interrupt is set by the

Am79C978A controller when a

read or write operation on the in-

ternal PHY management port is

complete from an internal opera-

tion. Examples of internal opera-

tions

are

Auto-Poll

PHY

Management

Port

generated

management frames. These are

normally hidden to the host.

AM79C978AVCW Datasheet(PDF) 121 Page - Advanced Micro Devices

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